32LDIP Search Results

UM62*512

Contextual Info: UM62L512 Series 6 4 K X 8 LOW VOLTAGE CMOS SRAM PRELIMINARY Features • Single + 3.3V power supply ■ Access times: 70/100 ns max. * Current: Low power version: Operating: 40mA ■ Directly TTL compatible: All inputs and outputs ■ Comm on I/O using three-state output

Contextual Info: UM23L4101 PRELIMINARY 524,288 X 8 BIT LOW VOLTAGE CMOS MASK ROM Features • ■ ■ ■ 524,288 x 8-bit organization Single +3V power supply Access time: 250 ns max. Current: Operating: 15mA (max.) Standby: 10 ¿¿A (max.) ■ Three-state outputs for wired-OR expansion

Contextual Info: UM23V8001 1,048,576 X 8 BIT WIDE VOLTAGE RANGE CMOS MASK ROM Features • 1,048,576 x 8 bit organization ■ Wide power supply range: + 2.7V to +5.5V ■ Access times: 150ns m ax. /VCC = 5V 250ns (m ax.)/VCC = 3V ■ Current: Operating: 50mA (m ax.)/VCC = 5V

UM621024B

Abstract: UM621024 um621024bm-70l
Contextual Info: UM621024B Seríes 128K X 8 CMOS SRAM Features • Single +5V power supply ■ Access times: 55/70 ns max. ■ Current: Low power version: Operating: 70mA Standby: 100(iA Very low power version: Operating: 70mA Standby: 25 (¿A * Full static operation, no clock or refreshing

UNITED MICROELECTRONICS CORPORATION

Abstract: UM621024 ic 7483 pin diagram UM621024C-10L UM621024CM-70LL ic 7483 ic 7483 pin configuration UM621024CM-70L IS81 UM621024C-70L
Contextual Info: co 5 •§ 2 co co co 03 i l 8 0Í il X ^ « O 1 X 5 a '1 0 H .-3 I3 5 i CM Co co 03 * ■n l ic ? s » 9 5 CNJ a- a ì S 5 5 o 2 c 5 a Iw ■ 3 O* * " I c <3 3 |? ! > - 55 ë x> u i i l i ■ ■ Î C «> c = •S w * >. « <* o ? 8 s„ :g ? 6 H- X3

UM62L4000M-70L

Contextual Info: UM62L4000 Series 512K X 8 LOW VOLTAGE CMOS SRAM P R E L IM IN A R Y Features • Single + 3.3V power supply ■ Access times: 70/100 ns max. ■ Current: Low power version: Operating: 40mA (max.) Standby: 100 ¡iA (max.) 1 Full static operation, no clock or refreshing

UM62L1024

Abstract: 32LDIP
Contextual Info: UM62L1024 Series 1 2 8 K X 8 LOW VOLTAGE CMOS SRAM PRELIMINARY Features • Single + 3.3V power supply ■ Access times: 70/100 ns max. ■ Current: Low power version: Operating: 40mA Standby: 50 uA Very low power version: Operating: 40mA Standby: 15 /iA

UM621024CM-70LL

Abstract: UM621024C-70LL M621024 UM621024CM-55L UM621024CM55LL
Contextual Info: UM621024C Series 1Z8K X 8 CMOS SRAM P R E L IM IN A R Y Features • Single +5V power supply ■ Access times: 55 /70 ns max. * Current: Low power version: Operating: 70mA Standby: 100 (iA Very low power version: Operating: 70mA Standby: 25 /¡A ■ Full static operation, no clock or refreshing

Contextual Info: 524,288 X 8 BIT CMOS MASK ROM Features 1524,288 x 8-bit organization 1Single +5V power supply i Access time: 120 ns max. 1Current: Operating: 40mA (max.) Standby: 30 iiA (max.) 1Three-state outputs forwired-OR expansion Mask Programmed for Chip Enable (Power-down) CE/ CE

DIP-32L

Contextual Info: UM62L1024A Seríes 128KX 8 LOW VOLTAGE CMOS SRAM Features • Single + 3.3V power supply * Access times: 70/100 ns max. ■ Current: Low power version: Operating: 40mA Standby: 50 iiA Very low power version: Operating: 40mA Standby: 15 uA ■ Full static operation, no clock or refreshing

Contextual Info: UM23L1101 131,072 X 8 BIT LOW VOLTAGE CMOS MASK ROM P R E L IM IN A R Y Features Three-state outputs for wired-OR expansion Full static operation TTL-compatible inputs and outputs Available in 32-pin DIP, 32-pin SOP packages or in DICE FORM 131,072 x 8 bit organization

UM23C2101

Abstract: UM23C21
Contextual Info: UM23C2101 262,144 X 8 BIT CMOS MASK ROM Features 1 262,144 x 8-bit organization 1 Single +5V power supply 1 Access time: 120 ns max. 1 Current: Operating: 30mA (max.) • Mask Programmed for Chip Enable (Power-down) C E / CE Output Enable O E /O E /N C ■ Full static operation

UM62512

Abstract: UM62512-70L UM62512M-70L m62512 DIP-32L
Contextual Info: UM62512 Series 64K X 8 CMOS SRAM PRELIMINARY Features • Single +5V power supply ■ Access times: 55 /70 ns max. ■ Current: Low power version: Operating: 70mA Standby: 1 0 0 M ■ Directly TTL compatible: All inputs and outputs ■ Comm on I/O using three-state output