32BLT Search Results

IMSG176/8

Contextual Info: TVP3027 VIDEO INTERFACE PALETTE XLAS106-MAY 1995 • Direct Interfacing to Video RAM • Supports Color Depths of 4-, 8-, 16-, 24-, and 32-Blt/Plxel • 64-Bit-Wide Pixel Bus • Supports Overscan For Creation of Custom Screen Borders • Color-Keyed Switching of Direct Color and

Contextual Info: TVP3026 VIDEO INTERFACE PALETTE X L A S 0 9 8 A - MAY 1995 | • Supports System Resolutions up to 1600 x 1280 at 76-Hz Refresh Rate • Versatile Pixel Bus Interface Supports Little- and Big-Endian Data Formats • Supports Color Depths of 4-, 8-, 16-, 24-,

Contextual Info: SN54AHC138, SN74AHC138 3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS S CLS258C - DECEM BER 1995 - REVISED JULY 1996 Operating Range 2-V to 5.5-V Vqc E P IC * Enhanced-Performance Implanted CMOS Process SN54AMC138 . . . J O R W PACKAGE SN74AHC138 . . . D, DB, N, OR PW PACKAGE

8087 data types

Abstract: 8087 coprocessor instruction set 8087 coprocessor architecture bcd addition program of 8086 intel 8087 architecture coprocessor intel 8087 amd 8086 8087 architecture and configuration 8284A clock generator driver 8086 interfacing of memory devices with 8086
Contextual Info: 8087 Numeric Data Coprocessor ÌAPX86 Family DISTINCTIVE CHARACTERISTICS • • • High perform ance arithm etic and transcendental fu n c­ tions in hardware Supports 8-, 16-, 32-, 64-bit integer Performs 32-, 64-, 80-bit floating point calculations conforming to !EEE standard

Contextual Info: 32-BIT CMOS ERROR DETECTION AND CORRECTION UNIT FEATURES: IDT49C460 IDT49C460A IDT49C460B IDT49C460C IDT49C460D IDT49C460E DESCRIPTION: • Fast Detect 10ns max. 12ns (max.) 16ns (max.) 25ns (max.) 30ns (max.) 40ns (max.) Correct 14ns (max.) 18ns (max.)

Contextual Info: w W 16-BIT CM O S ERROR DETECTION AND CO RRECTIO N UNIT IDT39C60A IDT ^ C6/2“ 1 IDT39C60 Inte3 rated Device Technology. Inc. MICROSLICE PRODUCT FEATURES: DESCRIPTION: • The IDT39C60 fam ily are high-speed, low-power, 16-bit Error De­ tection and Correction Units which generate check bits on a 16-bit

Contextual Info: ¡n tg l. 82596CA HIGH-PERFORMANCE 32-BIT LOCAL AREA NETWORK COPROCESSOR • Performs Complete CSMA/CD Medium Access Control MAC Functions— Independently of CPU — IEEE 802.3 (EOC) Frame Delimiting — HDLC Frame Delimiting ■ Supports Industry Standard LANs

CD 2399 GP

Abstract: 80387 DX Users Manual Programmers Reference
Contextual Info: PRByBJOODOÂIfflr in t e i Intel486 DX MICROPROCESSOR 168-Pin Grid Array Package High Performance Design — RISC Integer Core with Frequent Instructions Executing in One Clock — 25 MHz, 33 MHz, and 50 MHz Clock — 80, 106, 160 Mbyte/sec Burst Bus — CHMOS IV and CHMOS V Process

coprocessor

Contextual Info: in y Intel387 SX MATH COPROCESSOR N e w A u to m a tic P o w e r M a n a g e m e n t — L o w P o w e r C o n su m p tio n — T y p ic a lly 100 m A in D y n a m ic M o de, an d 4 m A in Id le M o d e S o c k e t C o m p a tib le w ith In te l3 8 7 Fam ily

Contextual Info: 80960RP 1.0 1.2 ABOUT THIS DOCUMENT Terminology In this document, the following terms are used: This data sheet contains ADVANCE INFORMATION about Intel’s i960 RP processor, including a func­ tional overview, mechanical data package signal locations and simulated thermal characteristics ,

Contextual Info: in te i 386 DX MICROPROCESSOR HIGH PERFORMANCE 32-BIT CHMOS MICROPROCESSOR WITH INTEGRATED MEMORY MANAGEMENT Optimized for System Performance — Pipelined Instruction Execution — On-Chip Address Translation Caches — 20, 25 and 33 MHz Clock — 40, 50 and 66 Megabytes/Sec Bus

Contextual Info: 32-BIT AND 64-BIT IEEE FLOATING-POINT MULTIPLIER AND ALU DESCRIPTION: FEATURES: T h e IDT721264 flo a tin g -p o in t m u ltip lie r and the IDT721265 flo a tin g -p o in t ALU p ro v id e h ig l^ p e e d 3 2-b it and 64-bit flo a tin g ­ p o in t p ro c e s s in g ca p a b ility .

Contextual Info: IME D INTEGRATED DEVICE • 4Ö2S771 0003^22 1 ■ 16-BIT CMOS ERROR DETECTION AND CORRECTION UNIT MICROSLICE PRODUCT FEATURES: • • ■ T -¥ £ -/7 Pin-compatible to all versions of the 2960 • Military product available compliant to MIL-STD-883, Class B

008 cow 734

Contextual Info: 80960CF-33, -25, -16 32-BIT HIGH PERFORMANCE SUPERSCALAR PROCESSOR • Socket and Object Code Compatible with 80960CA • Two Instructions/Clock Sustained Execution • Four 59 Mbytes/s DMA Channels with Data Chaining • Demultiplexed 3'2-bit Burst Bus with Pipelining

Contextual Info: HYM •HYUNDAI 1M X 532100A M-Series 32-blt CMOS DRAM MODULE DESCRIPTION The HYM532100A is a 1M x 32-bit R e t page mode CMOS ORAM module consisting of eight HY514400A in 20/26 pin SOJ on a 72 pin glass-epoxy printed circuit board. 0.22nF decoupling capacitor is mounted lo r each DRAM.

Contextual Info: 80960CF-40 32-BIT HIGH-PERFORMANCE SUPERSCALAR PROCESSOR • Socket and Object Code Compatible with 80960CA • Two Instructions/Clock Sustained Execution • Four 71 Mbytes/s DMA Channels with Data Chaining • Demultiplexed 32-Bit Burst Bus with Pipelining

hall marking code A04

Abstract: INTELDX4 write-through YSS 928
Contextual Info: INTEL486 PROCESSOR FAMILY • lntelDX4TM P ro c e s s o r — Up to 100-MHz Operation -Speed-M ultiplying Technology — 32-Bit Architecture — 16K-Byte On-Chip Cache — Integrated Floating-Point Unit — 3.3V Core Operation with 5V Tolerant I/O Buffers

Contextual Info: HYUNDAI HYM532100A M-Series 1M x 32-blt CM O S DRAM MODULE DESCRIPTION The HYM532100A is a 1M x 32-bit Fast page mode CMO S DRAM module consisting of eight HY514400A in 20/26 pin SOJ on a 72 pin glass-epoxy printed circuit board. 0.2^uF decoupling capacitor is mounted for each DRAM.

Cyrix FasMath

Abstract: CX-83S87 cyrix 386SX fcom 7c DATA SHEET FOR OL 107 E SOLDER PEST FasMath 83D87 386SX CIRCUIT diagram 80386 83S87
Contextual Info: 83S87 User’s Manual High Performance CMOS Math Processor CYRIX CORP 3bE » H SSñ^ñn □ GQDlB'ì fi • T—49—1 2-05 FasMath CX-83S87 User's Manual January, 1990 o * P.O. Box 850118 Richardson, TX 76085-0118 CYR CYRIX CORP 3bE D ■ 2 5 ö t filici □ □ D D I M Q

D70236

Contextual Info: NEC NEC Electronics Inc. Description The V53 is a high-speed, high-integration 16-bit CMOS microprocessor with a CPU that is object and source code compatible with the V20 /V30®. integrated on the same die is a 4-channel DMA controller, a UART, three timer/counters, an interrupt controller, a refresh

Contextual Info: ANALOG DEVICES □ 32/40-Bit IEEE Floating-Point DSP Microprocessor ADSP-21020 FE A T U R E S Superscalar IEEE Floating-Point Processor Off-Chip Harvard Architecture M axim izes Signal Processing Performance 30 ns, 33.3 M IP S Instruction Rate. Single-Cycle

AM29C33

Abstract: J-16
Contextual Info: Am 29C327 Double-Precision Floating-Point Processor FINAL DISTINCTIVE CHARACTERISTICS • • • • • H ig h -p e rfo rm a n ce d o u b le -p re c is io n flo a tin g -p o in t processor Comprehensive floating-point and integer instruction sets Single VLSI device performs single-, double-, and

Contextual Info: RC64474 RC64475™ Prelim inary RISController™ Embedded 64-bit Microprocessor, based on RISCore4000™ Features Implements MIPS-III Instruction Set Architecture ISA 3.3V I/O * High performance 64-bit microprocessor, based on the RISCore4000 Minimized branch and load delays, through streamlined

HYM532810

Abstract: HY5117400 HYM53
Contextual Info: ••HYUNDAI HYM532810 M-Series 8M X 32-blt CM O S DRAM MODULE DESCRIPTION The HYM532810 is a 8M x 32-bit Fast page mode C M O S DRAM module consisting of sixteen HY5117400 in 24/28 pin S O J on a 72 pin glass-epoxy printed circuit board. 0.22fi? decoupling capacitor is mounted for each DRAM,