317Q Search Results

GH1-317QB

Abstract: GH1-317QE GH1-317QY GH1-417QC GH1-417QF GH1-217QG GH1-217QH GH1-217QK GH1-217QX GH1-317QA
Contextual Info: 页码，1/1 GH1电感式接近开关 17 20 外形编号 检测距离Sn[mm] 具 备 型 号 NPN 常开 GH1-317QA NPN 常闭 GH1-317QB NPN 一开一闭 GH1-417QC DC PNP 常开 型 PNP 常闭 GH1-317QD GH1-317QE PNP 一开一闭 GH1-417QF 二线制 常开

m3351

Abstract: KD 2114 marking code J2UT 1203 6d t201 CY7C1339 EQUIVALENT cd 1031 cs
Contextual Info: CY7C1339 128K x 32 Synchronous-Pipelined Cache RAM Features The CY7C1339 I/O pins can operate at either the 2.5V or the 3.3V level; the I/O pins are 3.3V tolerant when V DDq=2.5V. * Supports 100-MHz bus fo r Pentium and PowerPC operations w ith zero w ait states

Contextual Info: fax id: 2052 :/ CYPRESS C Y M 1 8 5 1 V 3 3 1,024K x 32 3.3V Static RAM Module Features • High-density 3.3V 32-m egabit SRAM module • 32-bit Standard Footprint supports densities from 16K x 32 through 1 M x 32 • High-speed SRAMs — Access time of 12 ns

CY7C1350

Contextual Info: fax id: 1103 * g S S M ^ % rrv rt n n n CY7C1350 PRELIMINARY 128Kx36 Pipelined SRAM with NoBL Architecture F e a tu re s F u n c t io n a l D e s c r ip t io n • Pin compatible and functionally e q u iv a le n ts ZBT™ devices IDT71V546, MT55L128L36P and MCM63Z736

L133A

Contextual Info: CY7C1346 64K X 36 Synchronous-Pipelined Cache RAM Features The C Y 7 C 1 346 I/O pins can op era te at eith er the 2.5V o r the 3.3V level; the I/O pins are 3.3 V to le ra n t w h en V DDQ=2.5V. • Supports 10O-MHz bus for Pentium and PowerPC operations with zero wait states

2930D

Contextual Info: fax id: 1108 CY7C1338 :/ C Y P R E S S 128K X 32 Synchronous-Flow-Through 3.3V Cache RAM Features Functional Description • S u p p o rts 117-MHz m ic ro p ro c e s s o r cache s y s te m s w ith zero w a it states • 128K by 32 co m m o n I/O • Low S ta n d b y Pow er 1.65 mW, L v e rs io n

Contextual Info: PRELIMINARY CY82C692 Pentium hyperCache™ Chipset Data-Path/Integrated Cache for h C -VX, h C -D X Solutions Features Two-bit wraparound counter supporting Intel Burst or Linear burst sequence Supports 3-1-1-1 Level 2 cache operation up to 66 MHz bus speed

EQUIVALENT cd 1031 cs

Abstract: 7C1031
Contextual Info: CY7C1031 CY7C1032 PRELIM INARY 64K x 18 Synchronous Cache RAM • Direct interface with the processor and external cache controller • Asynchronous output enable • VOs capable of 33V operation • JEDEC-standard pinout • 52-pin PLCC and PQFP packaging

Contextual Info: ADVANCE 128K X 18, 64Kx 32/36 3.3V I/O, PIPELINED, DCD SYNCBURST SRAM MICRON I TECHNOLOGY, INC. SYNCBURST SRAM MT58LC128K18C6, MT58LC64K32C6, MT58LC64K36C6 3.3V Supply, Pipelined, Burst Counter and Double-Cycle Deselect FEATURES • Fast access times: 3.5ns, 3.8ns, 4.2ns, 4.5ns and 6ns

Contextual Info: mos IMS IMS IMS IMS IMS IMS 1605: 6 4 K x 1 1625: 1 6 K x 4 1629: 16K x 4 with Output Enable / 1626/7:16K x 4 with Separate I/Os 1635: 8K x 8 1695: 8K x 9 FEATURES • INMOS' Very High Speed Double Metal CMOS • Advanced Process-1.2 Micron Design Rules • 64K Bit Devices

Contextual Info: 128K X 18, 64Kx 32/36 3.3V I/O, PIPELINED, DCD SYNCBURST SRAM MICRON I TECHNOLOGY, INC. SYNCBURST SRAM MT58LC128K18C5, MT58LC64K32C5, MT58LC64K36C5 3.3V Supply, Pipelined, Burst Counter and Double-Cycle Deselect FEATURES • • • • • • • • •

Contextual Info: 4Mb: 256K x 18, 128K x 32/36 PIPELINED, DCD SYNCBURST SRAM MT58L256L18D, MT58L128L32D, MT58L128L36D 4Mb SYNCBURST SRAM 3.3V Vdd, 3.3V I/O, Pipelined, Double-Cycle Deselect FEATURES • • • • • • • • • • • • • • • Fast clock and OE# access times

qml-38535

Abstract: CDFP4-F16 GDIP1-T16
Contextual Info: REVISIONS LTR DESCRIPTION DATE APPROVED YR-M O-DA REV SHEET REV SHEET REV STATUS OF SHEETS REV SHEET 10 PREPARED BY Thanh V. Nguyen PMIC N/A S TA N D A R D M ICRO CIRC UIT DR A W IN G THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE

SAI60

Contextual Info: fax id: 2043 64K 128K 256K 512K Featu res x x x x 36 36 36 36 CYM9270 CYM9271A/B CYM9272A/B CYM9273 SRAM SRAM SRAM SRAM Module Module Module Module 9272A or 256K x 18 S R A M ’s 9272B, 9273). in plastic surface mount packages on an epoxy laminate board with pins. The

EOIZ

Contextual Info: CY7C1351 128Kx36 Flow-Through SRAM with NoBL Architecture Features Functional Description The CY7C1351 is a 3.3V 128K by 36 Synchronous Flow-Through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the

Contextual Info: fax id: 1083 C 'i- PRELIMINARY CY7C1021V30 64K Features X 16 Static RAM Writing to the device is accomplished by taking chip enable CE and write enable (WE) inputs LOW. If byte low enable (BEE) is LOW, then data from I/O pins (l/Oi through l/0 8), is written into the location specified on the address pins (A0

32K32C

Contextual Info: M I^ E a r n iM I 1M b 1 Mb: 64K x 18, 32K x 32/36 3.3V I/O, PIPELINED, DCD SYNCBURST SRAM S Y N C B U R S T ¡ S c a r c e SRAM w a ij M T58LC 32K32C 6' 3.3V Vdd, 3.3V I/O, Pipelined, Double-Cycle Deselect hw i FEATURES • Fast clock and OE# access times

"32K x 32" SRAM

Contextual Info: M I^ P r iM 8 I n'mmn'zSE£ 1 Mb: 64K x 18, 32K x 32/36 3.3V I/O, PIPELINED, DCD SYNCBURST SRAM 1Mb SYNCBURST MT58LC32K32C6' S R A M w a 3.3V V dd, 3.3V I/O, Pipelined, Double-Cycle Deselect FEATURES • Fast clock a n d OE# access tim es • Single +3.3V +0.3V/-0.165V p o w er su p p ly V d d

DS0075

Abstract: GAL22LV10C
Contextual Info: Lattice G A L 2 2 L V 1 0 C Low Voltage E2CMOS PLD Generic Array Logic ] Semiconductor I Corporation FEATURES • 3.3V LOW VOLTAGE 22V10 A rchitecture — Interfaces with Standard 5V TTL Devices — 45m A Typical Active C urrent 75m A Max. FUNCTIONAL BLOCK DIAGRAM

Contextual Info: 2Mb: 128K x 18, 64K x 32/36 PIPELINED, DCD SYNCBURST SRAM M IC R O N I TECHNOLOGY, INC. MT58LC128K18C6, MT58LC64K32C6, MT58LC64K36C6; MT58LC128K18F1, MT58LC64K32F1, MT58LC64K36F1 2Mb SYNCBURST SRAM 3.3V V d d , 3.3V or 2.5V I/O, Pipelined, Double-Cycle Deselect

Contextual Info: 128K x 18, 64K x 32/36 3.3V I/O, PI PELI NED, DCD S Y N C B U R S T SRAM MICRON I TECHNOLOGY, INC. C V K I P D I I D C O Y I M O D U n O CD O i l MT58LC128K18C5, MT58LC64K32C5, MT58LC64K36C5 T I A I UI n IV I 3.3V Supply, Pipelined, Double-Cycle Deselect Burst Counter and

Contextual Info: Lattice •■■■■■ GAL22LV10C Semiconductor Corporation Low Voltage E2CMOS PLD Generic Array Logic FEATURES FUNCTIONAL BLOCK DIAGRAM • 3.3V LOW VOLTAGE 22V 10 Architecture — Interfaces with Standard 5V TTL Devices — 45m A Typical Active C urrent 75m A Max.

Contextual Info: 128K x 8 3.3V SYNCHRONOUS SRAM LATE WRITE WITH ZBT AND FLOW-THROUGH OUTPUT ADVANCE INFORMATION IDT71V509 Integrated Device Technology, Inc. FEATURES: • • • • • • • 128K x 8 memory configuration High speed - 66 MHz 9 ns Clock-to-Data Access

Contextual Info: CY7C1347 128K x 36 Synchronous-Pipelined Cache RAM Features The CY7C1347 I/O pins can operate at either the 2.5V or the 3.3V level, the I/O pins are 3.3V tolerant when V DDQ=2.5V. • Supports 1 0O-MHz bus for Pentium and PowerPC operations with zero wait states