2M X 18 Search Results

Contextual Info: SIEMENS 3.3V 2M x 64-Bit SDRAM Module 3.3V 2M x 72-Bit SDRAM Module HYS64V2000GU HYS72V2000GU 168 pin unbuffered DIMM Modules Preliminary Information • 168 Pin JEDEC Standard, Unbuffered 8 Byte Dual-ln-Line SDRAM Module • 1 bank 2M x 64, 2M x 72 organisation

doz 112

Abstract: V2000G 235L
Contextual Info: SIEM EN S 3.3V 2M x 64-Bit SDRAM Module 3.3V 2M x 72-Bit SDRAM Module HYS64V2000GU HYS72V2000GU 168 pin unbuffered DIMM Modules Prelim inary Information • 168 Pin JEDEC Standard, Unbuffered 8 Byte Dual-ln-Line SDRAM Module • 1 bank 2M x 64, 2M x 72 organisation

Contextual Info: SIEM ENS 3.3V 2M x 64-Bit SDRAM Module 3.3V 2M x 72-Bit SDRAM Module HYS64V2000GU HYS72V2000GU 168 pin unbuffered DIMM Modules Prelim inary Inform ation • 168 Pin JEDEC Standard, Unbuffered 8 Byte Dual-In-Line SDRAM Module • 1 bank 2M x 64, 2M x 72 organisation

Contextual Info: SIEMENS 3.3V 2M x 64-Bit SDRAM Module 3.3V 2M x 72-Bit SDRAM Module HYS64V2100G C U-10 HYS72V2100G(C)U-10 168 pin unbuffered DIMM Modules Advanced Information • 168 Pin JEDEC Standard, Unbuffered 8 Byte Dual-In-Line SDRAM Module • 1 bank 2M x 64, 2M x 72 organisation

KM49RC2H-A60

Abstract: RDRAM CONCURRENT KM49RC2H samsung datecode samsung concurrent rdram RC2H-A66 concurrent RDRAM 72 9 concurrent rdram
Contextual Info: KM48RC2H/KM49RC2H Concurrent RDRAM 2M X 8 / 2 M x 9 Concurrent RDRAM Overview Ordering Information The 16 / 18Mbit Concurrent Rambus DRAMs RDRAM are Part No. Org. frequency KM49RC2H-A60 2M X 9 600Mhz extremely high-speed CMOS DRAMs organized as 2M words

HYS64V2100G

Contextual Info: 3.3V 2M x 64-Bit SDRAM Module 3.3V 2M x 72-Bit SDRAM Module HYS64V2100G C U-10 HYS72V2100G(C)U-10 168 pin unbuffered DIMM Modules Advanced Information • 168 Pin JEDEC Standard, Unbuffered 8 Byte Dual-In-Line SDRAM Module • 1 bank 2M x 64, 2M x 72 organisation

HYS64V2100G

Contextual Info: 3.3V 2M x 64-Bit SDRAM Module 3.3V 2M x 72-Bit SDRAM Module HYS64V2100G C U-10 HYS72V2100G(C)U-10 168 pin unbuffered DIMM Modules • 168 Pin JEDEC Standard, Unbuffered 8 Byte Dual-In-Line SDRAM Module for PC main memory applications • 1 bank 2M x 64, 2M x 72 organisation

Contextual Info: SIEMENS 3.3V 2M x 64-Bit SDRAM Module 3.3V 2M x 72-Bit SDRAM Module HYS64V2100G C U-10 HYS72V2100G(C)U-10 168 pin unbuffered DIMM Modules * 168 Pin JED EC Standard, Unbuffered 8 Byte Dual-In-Line SDRAM Module for PC main memory applications * 1 bank 2M x 64, 2M x 72 organisation

s2mX

Contextual Info: 3.3V 2M x 64-Bit SDRAM Module 3.3V 2M x 72-Bit SDRAM Module HYS64V2000GU HYS72V2000GU 168 pin unbuffered DIMM Modules Advanced Information • 168 Pin JEDEC Standard, Unbuffered 8 Byte Dual-ln-Line SDRAM Module • 1 bank 2M x 64, 2M x 72 organisation • Optimized for byte-write non-parity or ECC applications

Contextual Info: TS 35 x 7,5 terminal rail W 7,5 mm Terminal rails TS 35 x 7.5 Unperforated Material thickness Length 1 mm 2m Qty. 2m Order No. 0330800000 1 mm TS 35X7.5 1M/ST/ZN 16 mm2 1 mm 2m 2m 0383400000 1m 10 m 0383410000 Stainless steel TS 35X7.5 2M/CRN 16 mm2 1 mm 2m

4MX72 BIT SDRAM

Abstract: VS47217801BTGE VS2721
Contextual Info: VS27217801BTGE,VS47217801BTGE 2M,4MX72-Bit SDRAM Module VIS Description The VS27217801BTGE and VS47217801BTGE are 2M x 72 - bit and 4M x 72 - bit dual - in - line synchronous dynamic RAM module DIMM . It is mounted with 9/18 pieces of 2M x 8 synchronous DRAM(VG3617801BT), and each in a standard 44 pin TSOP package. The VS27217801BTGE and

Contextual Info: CY7C1317BV18 CY7C1319BV18 CY7C1321BV18 PRELIMINARY 18-Mbit DDR-II SRAM 4-Word Burst Architecture Features Functional Description • 18-Mbit density 2M x 8, 2M x 9, 1M x 18, 512K x 36 The CY7C1317BV18, CY7C1917BV18, CY7C1319BV18, and CY7C1321BV18 are 1.8V Synchronous Pipelined SRAM

Contextual Info: CY7C11461KV18, CY7C11571KV18 CY7C11481KV18, CY7C11501KV18 18-Mbit DDR II+ SRAM 2-Word Burst Architecture 2.0 Cycle Read Latency Features Functional Description • 18-Mbit Density (2M x 8, 2M x 9, 1M x 18, 512K x 36) ■ 450 MHz Clock for High Bandwidth

Contextual Info: CY7C11661KV18, CY7C11771KV18 CY7C11681KV18, CY7C11701KV18 18-Mbit DDR II+ SRAM 2-Word Burst Architecture 2.5 Cycle Read Latency Features Functional Description • 18-Mbit Density (2M x 8, 2M x 9, 1M x 18, 512K x 36) ■ 550 MHz Clock for High Bandwidth

IS61LPS204836B-200TQ

Abstract: IS61VVPS204836B-166B3L
Contextual Info: IS61LPS409618B, IS61LPS204836B, IS61LPS204832B, IS64LPS204836B, IS61VPS/VVPS409618B, IS61VPS/VVPS204836B 2M x 36, 2M x 32, 4M x 18 72 Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC RAM ADVANCED INFORMATION OCTOBER 2012 FEATURES DESCRIPTION • Internal self-timed write cycle

IBM0117800B2M

Abstract: IBM0117800P2M
Contextual Info: IBM0117800 2M x 811/10, 5.0V. IBM0117800P2M x 811/10, 3.3V, LP, SR. IBM0117800M 2M x 811/10, 5.0V, LP, SR. IBM0117800B2M x 811/10, 3.3V. IBM0117800 IBM0117800M IBM0117800B IBM0117800P 2M x 8 11/10 DRAM Features • 2,097,152 word by 8 bit organization • Single 3.3V ± 0.3V or 5.0V ± 0.5V power supply

Contextual Info: STI322000D1 -xxV 72-PIN DIMMS 2M X 32 DRAM DIMM Memory Module FEATURES GENERAL DESCRIPTION • The Simple Technology STI322000D1 is a 2M bits x 32 Dynamic RAM high density memory module. The Simple Technology STI322000D1 consist of four CMOS 2M x 8 DRAMs in 28-pin

Contextual Info: KM29V16000ATS ELECTRO NICS Flash 2M x 8 Bit NAND Flash Memory GENERAL DESCRIPTION FEATURES • Single 3.3 - volt Supply The KM29V16000ATS/RS is a 2M 2,097,152 x8 bit NAND • Organization - Memory Cell Array : (2M +64K)bit x 8bit - Data Register : (256 + 8)bit x 8bit

Contextual Info: CY7C11461KV18, CY7C11571KV18 CY7C11481KV18, CY7C11501KV18 18-Mbit DDR II+ SRAM 2-Word Burst Architecture 2.0 Cycle Read Latency Features Functional Description • 18-Mbit Density (2M x 8, 2M x 9, 1M x 18, 512K x 36) ■ 450 MHz Clock for High Bandwidth

Contextual Info: CY7C11661KV18, CY7C11771KV18 CY7C11681KV18, CY7C11701KV18 18-Mbit DDR II+ SRAM 2-Word Burst Architecture 2.5 Cycle Read Latency Features Functional Description • 18-Mbit Density (2M x 8, 2M x 9, 1M x 18, 512K x 36) ■ 550 MHz Clock for High Bandwidth

CY7C1317BV18

Abstract: CY7C1319BV18 CY7C1321BV18 CY7C1917BV18
Contextual Info: CY7C1317BV18 CY7C1917BV18 CY7C1319BV18 CY7C1321BV18 18-Mbit DDR-II SRAM 4-Word Burst Architecture Features Functional Description • 18-Mbit density 2M x 8, 2M x 9, 1M x 18, 512K x 36 The CY7C1317BV18, CY7C1917BV18, CY7C1319BV18, and CY7C1321BV18 are 1.8V Synchronous Pipelined SRAM

IS61LPS204832B

Contextual Info: IS61LPS409618B, IS61LPS204836B, IS61LPS204832B, IS64LPS204836B, IS61VPS/VVPS409618B, IS61VPS/VVPS204836B 2M x 36, 2M x 32, 4M x 18 72 Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC RAM ADVANCED INFORMATION FEBRUARY 2013 FEATURES DESCRIPTION • Internal self-timed write cycle

fast page mode dram controller

Abstract: IBM0117800B2M IBM0117800P2M
Contextual Info: IBM0117800 2M x 811/10, 5.0V. IBM0117800P2M x 811/10, 3.3V, LP, SR. IBM0117800M 2M x 811/10, 5.0V, LP, SR. IBM0117800B2M x 811/10, 3.3V. IBM0117800 IBM0117800M IBM0117800B IBM0117800P 2M x 8 11/10 DRAM Features • 2,097,152 word by 8 bit organization • Single 3.3V ± 0.3V or 5.0V ± 0.5V power supply

IBM0117800B2M

Abstract: IBM0117800P2M
Contextual Info: IBM0117800 2M x 811/10, 5.0V. IBM0117800P2M x 811/10, 3.3V, LP, SR. IBM0117800M 2M x 811/10, 5.0V, LP, SR. IBM0117800B2M x 811/10, 3.3V. IBM0117800 IBM0117800M IBM0117800B IBM0117800P 2M x 8 11/10 DRAM Features • 2,097,152 word by 8 bit organization • Single 3.3V ± 0.3V or 5.0V ± 0.5V power supply