28GBPS Search Results

28HP

Abstract: pcie gen3 10GBASE-KR class 10 up board Datasheet 2012 CPRI Multi Rate datasheets of optical fpgas germanium power devices corporation germanium small signal power devices corporation pcie X1 edge connector pcie X8
Contextual Info: Introducing Innovations at 28 nm to Move Beyond Moore’s Law WP-01125-1.1 White Paper In addition to processing techniques, FPGA innovations allow Altera to move beyond Moore’s Law to meet higher bandwidth requirements while meeting cost and power budgets. Altera’s Stratix V FPGAs provide breakthrough bandwidth via 28-Gbps

SFF-8665

Abstract: TIA-604-5
Contextual Info: WWW.PSM4.ORG 100G PSM4 Specification Parallel Single Mode 4 lane 9/15/2014 Version 2.0 September 15, 2014 100G PSM4 Specification This technical document has been created by the PSM4 MSA group. However it is not a warranted document, each transceiver supplier will have their own datasheet. If the user wishes to find a

Optical SAS QSFP

Abstract: CEI-6G-LR 28G-SR QSFP 32G CEI-11G QSFP QSFP CONNECTOR QSFP 25G ibis sata interlaken
Contextual Info: White Paper Extending Transceiver Leadership at 28 nm High-speed serial protocols with increased data rates and expanded capabilities are addressing the demand for more network bandwidth. Efficiently supporting the subsequent increase in system bandwidth by attaining higher data

tcam

Abstract: ternary content addressable memory 100GbE Altera Stratix V datasheets of optical fpgas 100g phy interlaken network processor receiver ber fec 100G 40GBASE-R 10Gbase-kr transmitter
Contextual Info: Addressing 100-GbE Line-Card Design Challenges on 28-nm FPGAs WP-01128-1.1 White Paper As various standard bodies finalize their 100G standards for transport, Ethernet, and optical interfaces, FPGAs play a vital role for early adopters of technology who want

SSTL-15

Abstract: SSTL15 5sgxa3 SSTL18 5SGX 610k k 552 642k mini-lvds RSDS 1517-pin
Contextual Info: Stratix V FPGA Family Package and I/O Selector Guide Stratix V FPGA Features The following features, packages, and I/O matrices give you an overview of our devices. To get the full story, check out our online selector guide: www.altera.com/selector. Stratix V GT, GX, GS, and E FPGAs 0.85 V , Up to 28-Gbps Transceivers1

Contextual Info: HMC854LC5 v01.0610 28 Gbps, 4:1 MUX WITH PROGRAMMABLE OUTPUT VOLTAGE MUX & DEMUX - SMT 3 Typical Applications Features The HMC854LC5 is ideal for: Differential & Singe-Ended Operation • SONET OC 192 Half Rate Clock Input • Broadband Test & Measurement

pcie gen3

Abstract: 28gbps
Contextual Info: Stratix V Device Handbook Volume 1: Overview and Datasheet Stratix V Device Handbook Volume 1: Overview and Datasheet 101 Innovation Drive San Jose, CA 95134 www.altera.com SV5V3-1.2 11.0 2011 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX are Reg. U.S. Pat.

HF35-F1152

Abstract: KF40-F1517 5sgxa3 eye-q 400 NF40-F1517 interlaken gf35 NF45 KF35-F1152
Contextual Info: Stratix V Device Family Overview January 2011 SV51001-1.6 SV51001-1.6 This document provides an overview of the Stratix V devices and their features. Many of these devices and features are enabled in the Quartus ® II software version 10.1. The remaining devices and features will be enabled in future versions of the

F1517

Abstract: KF40 5SGT GT 12 AR
Contextual Info: Migration Between Stratix V GX and Stratix V GT Devices AN-644-1.0 Application Note This application note provides guidelines for designing cross-family migration also known as vertical migration between Altera Stratix® V GX and Stratix V GT devices.

Contextual Info: HMC854LC5 v03.0413 MUX & DEMUX - SMT 3 28 Gbps, 4:1 MUX WITH PROGRAMMABLE OUTPUT VOLTAGE Typical Applications Features The HMC854LC5 is ideal for: Differential & Singe-Ended Operation • SONET OC 192 Half Rate Clock Input • Broadband Test & Measurement

HMC854LC5

Contextual Info: HMC854LC5 v01.0610 MUX & DEMUX - SMT 3 28 Gbps, 4:1 MUX WITH PROGRAMMABLE OUTPUT VOLTAGE Typical Applications Features The HMC854LC5 is ideal for: Differential & Singe-Ended Operation • SONET OC 192 Half Rate Clock Input • Broadband Test & Measurement

lpddr2 datasheet

Abstract: lpddr2 QSFP optical active cable D-type Connector 25 Pin UniPHY lpddr2 CCPD 33 CB 100MHz lpddr2 spec tsmc 28nm standard io library lpddr2 phy lpddr2 DQ calibration
Contextual Info: Stratix V Device Handbook 101 Innovation Drive San Jose, CA 95134 www.altera.com Software Version: Document Date: 10.0 July 2010 Copyright © 2010Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words

Altera Stratix V

Abstract: QSFP 40G transceiver CEI-28G interlaken optical 400G QSFP 400G M20K JTRS QSFP 10G
Contextual Info: Fulfilling Technology Needs for 40G–100G Network-Centric Operations and Warfare WP-01138-1.1 White Paper The development and deployment of network-centric operations and warfare NCOW to integrate and connect the military’s many separate networks relies on

MEGTRON 6

Abstract: AN-672
Contextual Info: Transceiver Link Design Guidelines for High-Gbps Data Rate Transmission 2013.02.15 AN-672 Subscribe Feedback As transceiver data rates increase and the unit interval time UI decrease, the end-to-end link design of a transceiver channel becomes increasingly critical to the overall performance of the link. Consider an Altera

pcie gen3

Abstract: 10GBASE-KR interlaken optical 400G CPRI multi rate 400G M20K 28Gbps 100g phy Stratix V
Contextual Info: Stratix V FPGAs: Built for Bandwidth Meeting Bandwidth Demands Mobile video, audio/video streaming, cloud computing—these are just a few of the many applications driving up bandwidth demands for the underlying communications infrastructure. To be successful, your next-generation products

Contextual Info: HMC854LC5 v04.0614 MUX & DEMUX - SMT 28 Gbps, 4:1 MUX WITH PROGRAMMABLE OUTPUT VOLTAGE Typical Applications Features The HMC854LC5 is ideal for: Differential & Singe-Ended Operation • SONET OC 192 Half Rate Clock Input • Broadband Test & Measurement Quarter Rate Reference Clock Output

v-by-one hs

Abstract: camera-link to 3G-SDI converter Netlogic camera-link to HDMI converter camera-link to hd-SDI converter serdes hdmi optical fibre SFP CPRI EVALUATION BOARD AL460A verilog SATA HDMI verilog code
Contextual Info: Version 8.0 Altera Product Catalog Contents Glossary. 2 Stratix FPGA series. .3 HardCopy® ASIC Series. 14 Arria® FPGA Series. 18

lpddr2 datasheet

Abstract: lpddr2 lpddr2 phy lpddr2 spec verilog code 8 bit LFSR in scrambler sgmii sfp cyclone SV51005-1 jesd79-3d lpddr2 DQ calibration QSFP CONNECTOR
Contextual Info: Stratix V Device Handbook 101 Innovation Drive San Jose, CA 95134 www.altera.com Software Version: Document Date: 10.1 January 2011 Copyright © 2011Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words

28-Gbps

Abstract: HMC854LC5
Contextual Info: HMC854LC5 v00.0510 28 Gbps, 4:1 MUX WITH PROGRAMMABLE OUTPUT VOLTAGE HIGH SPEED LOGIC - SMT 3 Typical Applications Features The HMC854LC5 is ideal for: Differential & Singe-Ended Operation • SONET OC 192 Half Rate Clock Input • Broadband Test & Measurement

100GBASE-R

Abstract: QSFP 40G transceiver 40GBASE-R CPRI multi rate gearbox pcie gen3 QSFP optical active cable QSFP M20K 5SGX
Contextual Info: Stratix V Device Family Overview SV51001-1.3 This document provides an overview of the Stratix V device features. Many of these features are enabled in the Quartus ® II software version 10.0. The remaining features will be enabled in future versions of the Quartus II software.

GPPO

Contextual Info: OPTICAL COMMUNICATION PRODUCT LINE “Providing integrated solution for 100 & 400Gbps Equipments” Providing Integrated Solutions for RF/Optical Assemblies New advanced 64 Gbps Mux & DeMux In QFN 5X5 mm package =

RF40-F1517

Abstract: KF40-F1517
Contextual Info: Stratix V Device Handbook Volume 1: Overview and Datasheet Stratix V Device Handbook Volume 1: Overview and Datasheet 101 Innovation Drive San Jose, CA 95134 www.altera.com SV5V3-1.3 11.0 2011 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX are Reg. U.S. Pat.