256BITS Search Results

Contextual Info: TE X AS INS TRUM E NTS - ADVANCE INFO R MAT ION Tiva TM4C1297NCZAD Microcontroller D ATA SH E E T D S -T M 4C 1297 NCZ A D- 1 5 8 0 2 . 2 7 2 9 S P M S 435A C o p yri g h t 2 0 07-2013 Te xa s In stru me n ts In co rporated Copyright Copyright © 2007-2013 Texas Instruments Incorporated. Tiva and TivaWare are trademarks of Texas Instruments Incorporated. ARM and Thumb are

Contextual Info: TE X AS INS TRUM E NTS - ADVANCE INFO R MAT ION Tiva TM4C129XKCZAD Microcontroller D ATA SHE E T D S -T M 4C 129XK CZ A D- 1 5 8 0 2 . 2 7 2 9 S P M S 448A C o p yri g h t 2 0 07-2013 Te xa s In stru me n ts In co rporated Copyright Copyright © 2007-2013 Texas Instruments Incorporated. Tiva and TivaWare are trademarks of Texas Instruments Incorporated. ARM and Thumb are

Contextual Info: TE X AS INS TRUM E NTS - ADVANCE INFO R MAT ION Tiva TM4C129CNCZAD Microcontroller D ATA SHE E T D S -T M 4C 129C NCZ A D- 1 5 8 0 2 . 2 7 2 9 S P M S 438A C o p yri g h t 2 0 07-2013 Te xa s In stru me n ts In co rporated Copyright Copyright © 2007-2013 Texas Instruments Incorporated. Tiva and TivaWare are trademarks of Texas Instruments Incorporated. ARM and Thumb are

verilog code for 32 bit AES encryption

Abstract: FIPS-197 SP800-38A EP3C40-6
Contextual Info: AES-P Programmable AES Encrypt/Decrypt Megafunction Conforms to the Advanced Encryption Standard AES standard (FIPS PUB 197) Single module efficiently integrates multiple AES functions and modes Run-time programmable for: − Encryption or Decryption − Cipher Key length:

SP800-38A

Abstract: FIPS-197 verilog code for 128 bit AES encryption verilog code for 32 bit AES encryption verilog code for AES algorithm verilog code for aes encryption
Contextual Info: Conforms to the Advanced Encryption Standard AES standard (FIPS PUB 197) AES-C Single module efficiently integrates multiple AES functions AES Optimized Encrypt/Decrypt Core Run-time programmable for: The AES-C core implements hardware data encryption and decryption using Rijndael

Contextual Info: TE X AS INS TRUM E NTS - ADVANCE INFO R MAT ION Tiva TM4C1292NCZAD Microcontroller D ATA SH E E T D S -T M 4C 1292 NCZ A D- 1 5 6 3 8 . 2 7 11 S P M S 432 C o p yri g h t 2 0 07-2013 Te xa s In stru me n ts In co rporated Copyright Copyright © 2007-2013 Texas Instruments Incorporated. Tiva and TivaWare are trademarks of Texas Instruments Incorporated. ARM and Thumb are

TM4C129LNCZAD

Contextual Info: TE X AS INS TRUM E NTS - ADVANCE INFO R MAT ION Tiva TM4C129LNCZAD Microcontroller D ATA SH E E T D S -T M 4C 129L NCZ A D- 1 5 6 3 8 . 2 7 11 S P M S 443 C o p yri g h t 2 0 07-2013 Te xa s In stru me n ts In co rporated Copyright Copyright © 2007-2013 Texas Instruments Incorporated. Tiva and TivaWare are trademarks of Texas Instruments Incorporated. ARM and Thumb are

Contextual Info: TE X AS INS TRUM E NTS - ADVANCE INFO R MAT ION Tiva TM4C1292NCPDT Microcontroller D ATA SH E E T D S -T M 4C 1292 NCP DT - 1 5 6 3 8 . 2 7 11 S P M S 431 C o p yri g h t 2 0 07-2013 Te xa s In stru me n ts In co rporated Copyright Copyright © 2007-2013 Texas Instruments Incorporated. Tiva and TivaWare are trademarks of Texas Instruments Incorporated. ARM and Thumb are

Contextual Info: DS2154 PRELIMINARY DALLAS SEMICONDUCTOR DS2154 Enhanced E1 Single Chip Transceiver PACKAGE OUTLINE FEATURES • Complete E1 CEPT PCM-30/ISDN-PRI transceiver functionality • Onboard long and short haul line interface for clock/ data recovery and waveshaping

Contextual Info: MEMORY CMOS 1 M x 16 BITS HYPER PAGE MODE DYNAMIC RAM MB8116165B-50/-60 CMOS 1,048,576 x 16 BITS Hyper Page Mode Dynamic RAM • DESCRIPTION The Fujitsu MB8116165B is a fully decoded CMOS Dynamic RAM DRAM that contains 16,777,216 memory cells accessible in 16-bit increments. The MB8116165B features a “hyper page” mode of operation whereby

LUPA-300

Abstract: CYIL1SM0300AA CYIL1SM0300AA-QBC L480 LUPA-1300 100 fps camera schematic LUPA300 CMOS global shutter
Contextual Info: LUPA-300 CYIL1SM0300AA-QBC VGA CMOS Image Sensor Features This VGA-resolution CMOS active pixel sensor features synchronous shutter and a maximal frame-rate of 250 fps in full resolution. The readout speed can be boosted by means of subsampling and windowed Region Of Interest ROI

Contextual Info: PRE LIM IN AR YMarch 1996 Edition 2.2 FUJITSU PRODUCT PROFILE SHEET MB8 1 1 6 1 6 0 A - 6 0 /- 7 0 CMOS 1M X 16BIT FAST PAGE MODE DYNAMIC RAM CMOS 1,048,576 x 16BIT Fast Page Mode Dynamic RAM The Fujitsu MB8116160A is a fully decoded CMOS Dynamic RAM DRAM that contains

P87/AD

Contextual Info: Ordering number : EN7972 LC875BP4A,LC875BM2A LC875BJ0A,LC875BH4A http://onsemi.com CMOS IC ROM 256K/224K/192K/176K byte, RAM 4096K byte on-chip 8-bit 1-chip Microcontroller Overview The LC875BP4A, LC875BM2A, LC875BJ0A, LC875BH4A is 8-bit single chip microcontroller with the following

Contextual Info: Ordering number : EN8298B LC87F5G32A CMOS IC FROM 32K byte, RAM 1024 byte on-chip http://onsemi.com 8-bit 1-chip Microcontroller Overview The SANYO LC87F5G32A is an 8-bit microcomputer that, centered around a CPU running at a minimum bus cycle time of 100ns, integrates on a single chip a number of hardware features such as 32K-byte flash ROM onboard

Contextual Info: -P R E L IM IN A R Y October 1995 Edition 1.1 = FUJITSU PRODUCT PROFILE SHEET MB 8 116165 A- 60/-70 CMOS 1M X 16BIT HYPER PAGE M O D E DYNAMIC RAM CMOS 1,048,576 x 16BIT Hyper Page Mode Dynamic RAM The Fujitsu MB8116165A is a fully decoded CMOS Dynamic RAM DRAM that contains

ibm25ppc750cxe

Abstract: dh28 code RISCwatch
Contextual Info: R Y PowerPC 750CXe RISC Microprocessor Datasheet February, 2001 PR EL IM IN A Version 1.0 for DD2.4 only IBM Microelectronics Division Notices Before using this information and the product it supports, be sure to read the general information on the back cover of this document.

Contextual Info: NM93CS06 MICROWIRE Bus Interface 256-Bit Serial EEPROM with Data Protect and Sequential Read General Description Features The NM93CS06 devices are 256 bits of CMOS non-volatile electrically erasable memory divided into 16 16-bit registers. Selected registers can be protected against data modification by

MB81V16165A

Contextual Info: To Top / Lineup / Index FUJITSU SEMICONDUCTOR DATA SHEET DS05-10192-3E MEMORY CMOS 1 M x 16 BITS HYPER PAGE MODE DYNAMIC RAM MB81V16165A-60/60L/-70/70L CMOS 1,048,576 × 16 BITS Hyper Page Mode Dynamic RAM • DESCRIPTION The Fujitsu MB81V16165A is a fully decoded CMOS Dynamic RAM DRAM that contains 16,777,216 memory

MB8116165A

Contextual Info: To Top / Lineup / Index FUJITSU SEMICONDUCTOR DATA SHEET DS05-10182-2E MEMORY CMOS 1M x 16 BIT HYPER PAGE MODE DYNAMIC RAM MB8116165A-60/-70 CMOS 1,048,576 × 16 BIT Hyper Page Mode Dynamic RAM • DESCRIPTION The Fujitsu MB8116165A is a fully decoded CMOS Dynamic RAM DRAM that contains 16,777,216 memory

celeron MOTHERBOARD CIRCUIT diagram

Abstract: socket 370 pinout AP-585 AP-589 CK-408 PGA370
Contextual Info: Distributed by: www.Jameco.com ✦ 1-800-831-4242 The content and copyrights of the attached material are the property of its owner. Intel Celeron® Processor for the PGA370 Socket up to 1.40 GHz on 0.13 Micron Process Datasheet Product Features • ■

200H

Abstract: C-002RX C-004R DS2404 DS2404B DS2404S
Contextual Info: DS2404 EconoRAM Time Chip www.dalsemi.com PIN ASSIGNMENT FEATURES § 4096 bits of nonvolatile dual-port memory including real time clock/calendar in binary format, programmable interval timer, and programmable power-on cycle counter § 1-WireTM interface for MicroLAN

Contextual Info: TE X AS INS TRUM E NTS - ADVANCE INFO R MAT ION Tiva TM4C129DNCZAD Microcontroller D ATA SHE E T D S -T M 4C 129D NCZ A D- 1 5 6 3 8 . 2 7 11 S P M S 440 C o p yri g h t 2 0 07-2013 Te xa s In stru me n ts In co rporated Copyright Copyright © 2007-2013 Texas Instruments Incorporated. Tiva and TivaWare are trademarks of Texas Instruments Incorporated. ARM and Thumb are

intel Socket 775 VID VTT

Abstract: 775 MOTHERBOARD CIRCUIT diagram intel 775 motherboard diagram socket AM2 pinout socket pga370
Contextual Info: Intel Pentium® III Processor Based on 0.13 Micron Process Up to 1.33 GHz Datasheet • ■ ■ ■ ■ ■ ■ ■ Available at 1.0, 1.13, 1.20, 1.33 GHz. System bus frequency at 133 MHz 256 KB Advanced Transfer Cache on-die, full speed Level 2 (L2 cache with Error

SHA256

Abstract: Atmel tape and reel spec 8-lead SOIC
Contextual Info: Atmel AT88SA102S Atmel CryptoAuthentication Product Authentication Chip DATASHEET Not Recommended for New Designs Replaced by ATSHA204 Features • • • • • • • • • • • Secure authentication and key exchange Superior SHA-256 hash algorithm