256KX8 Search Results

Contextual Info: OJ bq4014/bq4014Y UNITRODE- 256Kx8 Nonvolatile SRAM Features > Data retention in the absence of power > Automatic write-protection dur­ ing power-up/power-down cycles >• Industry-standard 32-pin 256K x 8 pinout >• Conventional SEAM operation; unlimited write cycles

UNITRODE

Contextual Info: bq4014/bq4014Y 256Kx8 Nonvolatile SRAM Features ➤ Data retention in the absence of power ➤ Automatic write-protection during power-up/power-down cycles ➤ Industry-standard 32-pin 256K x 8 pinout ➤ Conventional SRAM operation; unlimited write cycles

K6F2008S2E

Abstract: K6F2008S2E-F
Contextual Info: K6F2008S2E Family CMOS SRAM Document Title 256Kx8 bit Super Low Power and Low Voltage Full CMOS Static RAM Revision History Revision No. History Draft Date Remark Preliminary 0.0 Initial Draft February 28, 2001 1.0 Finalize September 27, 2001 Final The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and

Contextual Info: bq4014/bq4014Y 256Kx8 Nonvolatile SRAM Features General Description ➤ Data retention in the absence of power The CMOS bq4014 is a nonvolatile 2,097,152-bit static RAM organized as 262,144 words by 8 bits. The integral control circuitry and lithium energy

bq4014

Abstract: BQ4014MB-120 BQ4014MB-85 bq4014Y BQ4014YMB-85
Contextual Info: bq4014/bq4014Y 256Kx8 Nonvolatile SRAM Features General Description ➤ Data retention in the absence of power The CMOS bq4014 is a nonvolatile 2,097,152-bit static RAM organized as 262,144 words by 8 bits. The integral control circuitry and lithium energy

WED8L24257V

Abstract: DSP5630X
Contextual Info: WED8L24257V Asynchronous SRAM, 3.3V, 256Kx24 FEATURES DESCRIPTION n 256Kx24 bit CMOS Static The WED8L24257VxxBC is a 3.3V, twelve megabit SRAM constructed with three 256Kx8 die mounted on a multi-layer laminate substrate. With 10 to 15ns access times, x24 width and a 3.3V

555H

Abstract: MX29F200B MX29F200T
Contextual Info: MX29F200T/B 2M-BIT [256Kx8/128Kx16] CMOS FLASH MEMORY FEATURES • • • • • • • • • 5.0V±10% for read, erase and write operation 131072x16/262144x8 switchable Fast access time: 55/70/90/120ns Low power consumption - 40mA maximum active current@5MHz

Contextual Info: W D _ EDI8F8259C i Electronic Dettgn« Inc. i Commercial Two Megabit SRAM Module 256Kx8 Static RAM CMOS, Module Features The EDI8F8259C is a 2 megabit CMOS Static RAM based on two high speed 256Kx4 Static RAMs mounted on a multi-layered epoxy laminate FR4 substrate.

Contextual Info: WDÌ EDI8F8259C ELECTRONIC DESIGNS INC. • High Speed Two Megabit SRAM Module Features 256Kx8 Static RAM CMOS, Module The EDI8F8259C is a 2 megabit CMOS Static RAM based on two high speed 256Kx4 Static RAMs mounted on a mutti-layered epoxy laminate FR4 substrate.

Contextual Info: Preliminary l3C|4014/bC|4014 Y 256Kx8 Nonvolatile SRAM Features > Data retention in the absence of power > Automatic write-proteddon during power-up/power-down cycles > Industry-standard 32-pin 256K x 8 pinout > Conventional SRAM operation; unlimited write cycles

Contextual Info: DPS256P8 Dense-Pac Microsystems. Inc. 256K X 8 CMOS SRAM MODULE O DESCRIPTION: The DPS256P8 is a fully static asynchronous Static Random Access M em o ry SRAM and is organized as 256KX8. The m odule consists o f eight 32K X 8 C M O S SRAMs surface m ounted to an epoxy lam inate (FR4) substrate.

Contextual Info: EDI8M8256C70/100/120PC ^EDI High Performance 2 Megabit SRAM Module 256Kx8 Static RAM CMOS, Module Features The EDI8M8256C is a 2048K bit CMOS Static RAM module. It is based on eight 32Kx8 Static RAMs in plastic VSOP packages mounted on a multi-layered ceramic

Contextual Info: EDI8M8257C 90/100/120/150 Module The fu tu re . . . today, i ÄDWÄNKgE DIMFÛI^IMIÂTDÛINI 256Kx8 SRAM CMOS, High Speed Module Features The EDI8M8257C is a 2048K 256Kx8 bit High Speed Static RAM module constructed using two EDI88128C (128Kx8) Static RAMs In teadless chip

Contextual Info: Preliminary information •■ AS29F200 I I 5V 256KX8/128Kx 16 CMOS Flash EEPROM Features • Organization: 256Kx8 or 128K xl6 • Sector architecture - One 16K; two 8K; one 32K; and three 64K byte sectors - Boot code sector architecture—T top or B (bottom)

Contextual Info: CAT25AM02 2 Mb SPI Serial CMOS EEPROM Description The CAT25AM02 is a 2M−bit Serial CMOS EEPROM device internally organized as 256Kx8 bits. This features a 256−byte page write buffer and supports the Serial Peripheral Interface SPI protocol. The device is enabled through a Chip Select (CS) input. In

Contextual Info: MX29F200T/B 2M-BIT [256Kx8/128Kx16] CMOS FLASH MEMORY FEATURES • • • • • • • • • 5.0V±10% for read, erase and write operation 131072x16/262144x8 switchable Fast access time: 55/70/90/120ns Low power consumption - 40mA maximum active current@5MHz

Contextual Info: NanoAmp Solutions, Inc. 670 North McCarthy Blvd. Suite 220, Milpitas, CA 95035 ph: 408-935-7777, FAX: 408-935-7770 www.nanoamp.com N02M083WL1A 2Mb Ultra-Low Power Asynchronous Medical CMOS SRAM 256Kx8 bit Overview Features The N02M083WL1A is an integrated memory

29F200T

Contextual Info: MX29F200T/B 2M-BIT [256Kx8/128Kx16] CMOS FLASH MEMORY FEATURES • • • • • • • • • 5.0V±10% for read, erase and write operation 131072x16/262144x8 switchable Fast access time: 55/70/90/120ns Low power consumption - 40mA maximum active current@5MHz

K6F2008U2E

Abstract: K6F2008U2E-EF55 K6F2008U2E-EF70 K6F2008U2E-YF55 K6F2008U2E-YF70 1024 256x8 SRAM
Contextual Info: K6F2008U2E Family CMOS SRAM Document Title 256Kx8 bit Super Low Power and Low Voltage Full CMOS Static RAM Revision History Revision No. History Draft Date Remark Preliminary 0.0 Initial Draft February 28, 2001 1.0 Finalize September 27, 2001 Final 2.0 Revise

Contextual Info: bq4014/bq4014Y 256Kx8 Nonvolatile SRAM Features General Description ➤ Data retention in the absence of power The CMOS bq4014 is a nonvolatile 2,097,152-bit static RAM organized as 262,144 words by 8 bits. The integral control circuitry and lithium energy

3QA18

Abstract: 3UA18
Contextual Info: 256Kx8 ROM/32Kx8 SRAM Combo Memory DP50CM232-E M í C \i O S Y S T E M S DESCRIPTION: The DP50CM232-E is a combination memory chip consist of 2M-bit Read Only Memory organized as 256K words by 8 bits and a 256K-bit Static Random Access Memory organized as 32K words by 8 bits.

HY62U8200LST

Contextual Info: HY62V8200- I /HY62U8200-(I) Series 256Kx8bit CMOS SRAM DESCRIPTION FEATURES The HY62V8200-(I)/HY62U8200-(I) is a high speed, low power and 2M bit CMOS SRAM organized as 262,144 words by 8bit. The HY62V8200-(I) / HY62U8200-(I) uses high performance CMOS process technology and

Contextual Info: K6F2008V2M, K6F2008S2M, K6F2008R2M Family CMOS SRAM Document Title 256Kx8 bit Super Low Power and Low Voltage Full CMOS Static RAM Revision History Revision No. History Draft Date Remark 0.0 Initial draft October 2, 1996 Advance 0.1 Revise - Remove sTSOP1 from product

EDI88257CA

Abstract: EDI88512CA
Contextual Info: EDI88257CA White Electronic Designs 256Kx8 Monolithic SRAM FEATURES The EDI88257CA is a 2 Megabit 256Kx8 bit Monolithic CMOS Static RAM. „ Access Times of 20, 25, 35, 45, 55ns „ Data Retention Function LPA Versions „ TTL Compatible Inputs and Outputs