238Q Search Results

238Q

Abstract: OP191GP VRS transformer 44-PIN ADS-238Q OPA642
Contextual Info: ® ADS-238Q 12-Bit, 20MHz, Low Power Sampling A/D Converters INNOVATION and EXCELLENCE FEATURES • · · · · · · 20MHz sampling rate Low Power, 100mW, max 100MHz full power input bandwidth Integral sample-and-hold Single +3V supply operation TTL compatible digital output

Contextual Info: UltraLogic 128-Macrocell Flash CPLD is designed to bring th e ease o f use and high perform ance o f th e 22V10 to highdensity CPLDs. Features • 128 macrocells in eight logic blocks • 64 I/O pins T he 128 m acrocells in th e CY7C374 are di­ vided betw een eight logic blocks. Each

Contextual Info: PLDC20G10B/PLDC20G10 CYPRESS Features • Fast — Commercial: tpp - 15 ns, tc o — 10 ns, tg = 12 ns — Military: tpp = 20 ns, tc o = 15 ns, tg = 15 ns CMOS Generic 24-Pin Reprogrammable Logic Device • Generic architecture to replace stan­ dard logic functions including: 20L10,

Contextual Info: CY7C372 PRELIMINARY CYPRESS SEMICONDUCTOR 64-Macrocell Flash PLD Features Functional Description • 64 macrocells in four logic blocks • 32 I/O pins • 6 dedicated inputs including 2 clock pins • No hidden delays • High speed The CY7C372 is a Flash Erasable Pro­

Contextual Info: w ~ CYPRESS Features • 32 macrocells in two logic blocks • 32 I/O pins • 6 dedicated inputs including 2 clock pins • In-System Reprogrammable ISR Flash technology — JTAG interface • No hidden delays • High speed — f M A X = 143 MHz — tpD= 8*5 ns

Contextual Info: UltraLogic 64-Macrocell Flash CPLD Features Functional Description • 64 m acrocells in four logic blocks T h e CY7C373 is a Flash erasable Com plex Program m able Logic Device C PL D and is p a rt o f th e F lash 370 ” family o f highdensity, high-speed C PLD s. Like all m em ­

319S2

Contextual Info: WFw CYPRESS CY7C374Ì ADVANCED INFORMATION UltraLogic 128-Macrocell Flash CPLD Features • 128 macrocells in eight logic blocks • 64 I/O pins • 6 dedicated inputs including 4 clock pins • In-System Reprogrammable ISR™ Flash technology — JTAG interface

Contextual Info: 32-Macrocell Flash CPLD Features Functional Description • 32 macrocells in two logic blocks The CY7C371 is a Flash erasable Complex Programmable Logic Device CPLD and is part of the F lash370 ” family of highdensity, high-speed CPLDs. Like all mem­

allocator

Contextual Info: CY7C373Ì PRELIMINARY UltraLogic 64-Macrocell Flash CPLD Features Device CPLD and is part of the FLASH370i™ family of high-density, high­ speed CPLDs. Like all members of the F lash 37(H family, the CY7C373i is de­ signed to bring the ease of use and high

Contextual Info: fax id: 5015 •vvrMWW>>>>>>>>wwvi CY7C9335 SMPTE-259M/DVB-ASI Descrambler/Framer-Controller Features • Fully compatible with SMPTE-259M-BCD — SMPTE-125M com pliant for 4:2:2 component video — SMPTE-244M com pliant for 4fsc composite video • Fully compatible with DVB-ASI

Contextual Info: fax id: 5015 CY7C9335 SMPTE-259M/DVB-ASI Descrambler/Framer-Controller SMPTE-259M compatible high-speed serial data stream into 10-bit parallel characters. Featu res • Fully compatible with SMPTE-259M — SMPTE-125M com pliant for 4:2:2 component video This device performs both TRS sync detection and framing,

Contextual Info: y PLDC20G10B/PLDC20G10 CYPRESS Features • Fast — Commercial: tpo = 15 ns, tco — 10 ns, ts = 12 ns — Military: tpo = 20 ns, tco = 15 ns, ts = 15 ns • Low power — Ice max.: 70 mA, commercial — Ice max.: 100 mA, military • Commercial and military temperature

C1573

Abstract: sim 300
Contextual Info: Miuiouay, úo^ioiiiuvi tn, 199& Revision: Tuesday, December 22,1992 •fi»«* n i W «! S7E D 5 5 5 ^ 2 C YP RE S S SEMI CONDUCTOR ODDTOMl ICYP 3bl CY7C375 PRELIMINARY CYPRESS SEMICONDUCTOR 128-Macrocell FLASH PLD Features Functional Description • 128 macroceils in eight logic blocks

Contextual Info: fax id: 6137 CY7C372Î C'i- UltraLogic 64-Macrocell Flash CPLD Features FLASH370i™ family of high-density, high-speed CPLDs. Like all members of the Fi_ASH370i family, the CY7C372i is de­ signed to bring the ease of use and high performance of the 22V10, as well as PCI Local Bus Specification support, to

CY37512

Contextual Info: UltraLogic 512-Macrocell ISR™ CPLD Features — tco = 6 ns • Product-term clocking • IEEE 1149.1 JTAG boundary scan • 512 macrocells in 32 logic blocks • In-System Reprogrammable™ ISR™ — JTAG-compliant on-board programming • Programmable slew rate control on individual l/Os

Contextual Info: Features « 128 macrocells in eight logic blocks • 64 I/O pins • 6 dedicated inputs including 4 clock pins • No hidden delays • High speed — fMAx = 100 MHz — tpo = 12 ns — ts = 7 ns " tco = 7 ns • Electrically Alterable Flash technology • Available in 84-pin PLCC, 84-pin

Contextual Info: CY7C372 PRELIMINARY CYPRESS 64-Macrocell Flash CPLD Features Functional Description • 64 macrocells in four logic blocks • 32 I/O pins • 6 dedicated inputs including 2 clock pins • No hidden delays • High speed — fMAX - 125 MHz — tpD - 10 ns

P10CF-10PC

Contextual Info: PAL22V10CF _ PAL22VP10CF ^ SEMICONDUCTOR Features • Ultra high speed supports today’s and tomorrow’s fastest microprocessors — tpo = 7.5 ns — t§u = 3 ns — fM AX — 2 new feedback paths PAL22VP10CF • Synchronous PRESET, asynchronous

tlO41

Abstract: 7C373-125 CY7C373 CY7C374 FLASH370 Wo2c
Contextual Info: CYPRESS Features • 64 macrocells in four logic blocks • 64 I/O pins • 6 dedicated inputs including 4 clock pins • No hidden delays • High speed — f M A X = 12S MHz — tpo = 10 ns — ts = 5.5 ns — tc o = 6-5 ns • Electrically alterable Flash

Contextual Info: 7C372: Wednesday, September 23,1992 Revision: Monday, January 4,1993 57E D m 550*^2 SbO CYPRESS SEMICONDUCTOR 'T 'A í - ñ - o i CY7C372 PRELIMINARY «sar CYPRESS . SEMICONDUCTOR ICYP 64-Macrocell Flash PLD Features Functional Description • 64 macrocells in four logic blocks

logic block diagram of cypress flash 370 device

Abstract: cypress flash 370 device SEM03 features cypress flash 370 7C371-2
Contextual Info: 7C373: Thursday, September 24,1992 .Revision: Monday,January4,1993 S7E D • 2 5 f l T L > t iE 00CH031 41E CYPRESS SEMICONDUCTOR ^ ^ s ts s s s 'Z ^ ^ i is m = ^ 'T'^' ci- PRELIMINARY Q Y PR ESS . • 128 macrocells in eight logic blocks

NCL025

Contextual Info: •■■■■■■\fct>cw.-. s a s iâ s ^ 5^” .w s & v PRELIMINARY _ . "T U ltra 3 7 5 1 2 UltraLogic 512-Macrocell ISR™ CPLD Features • • • • • 512 macrocells in 32 logic blocks • In-System Reprogrammable™ ISR™ — JTAG-compliant on-board programming

SMPTE-244M

Contextual Info: -"• s.* .MF j r * r CY7C9235 SMPTE-259M/DVB-ASI Scrambler/Controller a CY7B9234 HOTLink transmitter, which then converts the bit-parallel characters into a SMPTE-259M compatible high-speed serial data stream. Features • Fully compatible with SMPTE-259M

Contextual Info: C Y7C375i p vp v « *1 X X UltraLogic 128-Macrocell Flash CPLD Features * 1 28 macro cells in eig ht logic blo cks * 1 28 I/O pins * 5 dedicated inp u ts in c lu d in g 4 clock pins * In-System R e p ro g ra m m a b le ISR™ Flash tech n o lg y * JTAG interface