236Q Search Results

CY101E383

Abstract: diode SKE 39
Contextual Info: W r CY10E383 CY101E383 CYPRESS ECL/TTL/ECL Translator and High-Speed Bus Driver Features Functional Description • B iC M O S for optim um speed/power • H igh speed max. — 2.5 n s Ipu TTL-to-EC L — 3.5 n s tpo EC L-to-TTL The CY10/101E383 is a new-generation

Contextual Info: 7 PLD20G10C C YPRESS • Features • Ultra high speed supports today’s and tomorrow’s fastest microprocessors Generic 24-Pin PAL Device 10 user-programmable output macrocells — Output polarity control — Registered or combinatorial operation — tpo = 7.5 ns

Contextual Info: UltraLogic 128-Macrocell Flash CPLD is designed to bring th e ease o f use and high perform ance o f th e 22V10 to highdensity CPLDs. Features • 128 macrocells in eight logic blocks • 64 I/O pins T he 128 m acrocells in th e CY7C374 are di­ vided betw een eight logic blocks. Each

Contextual Info: PLDC20G10B/PLDC20G10 CYPRESS Features • Fast — Commercial: tpp - 15 ns, tc o — 10 ns, tg = 12 ns — Military: tpp = 20 ns, tc o = 15 ns, tg = 15 ns CMOS Generic 24-Pin Reprogrammable Logic Device • Generic architecture to replace stan­ dard logic functions including: 20L10,

Contextual Info: CY7C372 PRELIMINARY CYPRESS SEMICONDUCTOR 64-Macrocell Flash PLD Features Functional Description • 64 macrocells in four logic blocks • 32 I/O pins • 6 dedicated inputs including 2 clock pins • No hidden delays • High speed The CY7C372 is a Flash Erasable Pro­

Contextual Info: w ~ CYPRESS Features • 32 macrocells in two logic blocks • 32 I/O pins • 6 dedicated inputs including 2 clock pins • In-System Reprogrammable ISR Flash technology — JTAG interface • No hidden delays • High speed — f M A X = 143 MHz — tpD= 8*5 ns

Contextual Info: UltraLogic 64-Macrocell Flash CPLD Features Functional Description • 64 m acrocells in four logic blocks T h e CY7C373 is a Flash erasable Com plex Program m able Logic Device C PL D and is p a rt o f th e F lash 370 ” family o f highdensity, high-speed C PLD s. Like all m em ­

319S2

Contextual Info: WFw CYPRESS CY7C374Ì ADVANCED INFORMATION UltraLogic 128-Macrocell Flash CPLD Features • 128 macrocells in eight logic blocks • 64 I/O pins • 6 dedicated inputs including 4 clock pins • In-System Reprogrammable ISR™ Flash technology — JTAG interface

Contextual Info: 32-Macrocell Flash CPLD Features Functional Description • 32 macrocells in two logic blocks The CY7C371 is a Flash erasable Complex Programmable Logic Device CPLD and is part of the F lash370 ” family of highdensity, high-speed CPLDs. Like all mem­

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allocator

Contextual Info: CY7C373Ì PRELIMINARY UltraLogic 64-Macrocell Flash CPLD Features Device CPLD and is part of the FLASH370i™ family of high-density, high­ speed CPLDs. Like all members of the F lash 37(H family, the CY7C373i is de­ signed to bring the ease of use and high

Contextual Info: y PLDC20G10B/PLDC20G10 CYPRESS Features • Fast — Commercial: tpo = 15 ns, tco — 10 ns, ts = 12 ns — Military: tpo = 20 ns, tco = 15 ns, ts = 15 ns • Low power — Ice max.: 70 mA, commercial — Ice max.: 100 mA, military • Commercial and military temperature

22V10G-7

Contextual Info: m f CYPRESS Features — f[HAX = 1 6 6 MHz External • Reduced ground bounce and under­ shoot • PLCC and LCC packages w ith addi­ tional Vc c and V ss pins for lowest ground bounce • Up to 22 inputs and 10 outputs for more logic power Synchronous PRESET, asynchronous

C1573

Abstract: sim 300
Contextual Info: Miuiouay, úo^ioiiiuvi tn, 199& Revision: Tuesday, December 22,1992 •fi»«* n i W «! S7E D 5 5 5 ^ 2 C YP RE S S SEMI CONDUCTOR ODDTOMl ICYP 3bl CY7C375 PRELIMINARY CYPRESS SEMICONDUCTOR 128-Macrocell FLASH PLD Features Functional Description • 128 macroceils in eight logic blocks

37-25615

Abstract: CY37256 CY37256P160-125UMB
Contextual Info: UltraLogic 256-Macrocell ISR™ CPLD Features — tCo = 4 -5 ns • Product-term clocking • IEEE 1149.1 JTAG boundary scan • 256 macrocells in sixteen logic blocks • In-System Reprogrammable ISR™ — JTAG-compliant on-board programming • Programmable slew rate control on individual l/Os

Contextual Info: fax id: 5000 CY101E383 ECL/TTL/ECL Translator and High-Speed Bus Driver Featu res • B iC M O S for optimum speed/p ow er • High speed max. — 3.0 ns tpD TTL-to-ECL — 4 ns t PD ECL-to-TTL • Low skew < ± 1 ns • Can o perate on single +5V supply

CY37512

Contextual Info: UltraLogic 512-Macrocell ISR™ CPLD Features — tco = 6 ns • Product-term clocking • IEEE 1149.1 JTAG boundary scan • 512 macrocells in 32 logic blocks • In-System Reprogrammable™ ISR™ — JTAG-compliant on-board programming • Programmable slew rate control on individual l/Os

Contextual Info: Features « 128 macrocells in eight logic blocks • 64 I/O pins • 6 dedicated inputs including 4 clock pins • No hidden delays • High speed — fMAx = 100 MHz — tpo = 12 ns — ts = 7 ns " tco = 7 ns • Electrically Alterable Flash technology • Available in 84-pin PLCC, 84-pin

Contextual Info: CY7C372 PRELIMINARY CYPRESS 64-Macrocell Flash CPLD Features Functional Description • 64 macrocells in four logic blocks • 32 I/O pins • 6 dedicated inputs including 2 clock pins • No hidden delays • High speed — fMAX - 125 MHz — tpD - 10 ns

lmw14

Contextual Info: PLDC20G10B/PLDC20Gt0 i f C Y PR ESS CMOS Generic 24-Pin Reprogrammable Logic Device F ea tu res • Fast — C om m ercial: Ip» = 15 n s, t o = 10 n s, l s = 12 ns — M ilitary: tpu = 20 n s, t( <> = *5 n s, ts = 15 ns • G eneric arch itectu re to replace sta n ­

PALCE22V10D

Abstract: L-120 AB
Contextual Info: C palce 22vio ypress Flash Erasable, Reprogrammable CMOS PAL Device Features • F unctional D escription 3 n s ts 5 n s tpu 181-M H z sta te m ach in e Low power — 90 mA m ax. com m ercial 10 ns — 10 n s m ilitary a n d in d u stria l ver­ sio n s

Contextual Info: Technische Information / technical information IGBT-Module IGBT-modules DDB6U25N16VR Vorläufige Daten / preliminary data Diode-Gleichrichter / diode-rectifier Höchstzulässige Werte / maximum rated values A325EF36!F"#6$1B%3DE1322E14DDD &' 6 6*+,

tlO41

Abstract: 7C373-125 CY7C373 CY7C374 FLASH370 Wo2c
Contextual Info: CYPRESS Features • 64 macrocells in four logic blocks • 64 I/O pins • 6 dedicated inputs including 4 clock pins • No hidden delays • High speed — f M A X = 12S MHz — tpo = 10 ns — ts = 5.5 ns — tc o = 6-5 ns • Electrically alterable Flash

Contextual Info: 7C372: Wednesday, September 23,1992 Revision: Monday, January 4,1993 57E D m 550*^2 SbO CYPRESS SEMICONDUCTOR 'T 'A í - ñ - o i CY7C372 PRELIMINARY «sar CYPRESS . SEMICONDUCTOR ICYP 64-Macrocell Flash PLD Features Functional Description • 64 macrocells in four logic blocks