215 BGA Search Results

T25 4 h5

Abstract: AE23 AF23 EP20K60E 356-pin 215 bga BGA128
Contextual Info: EP20K60E I/O Pins ver. 1.1 I/O & VREF Bank 8 8 8 8 – 8 8 8 8 8 – 8 – Pad Number Orientation Pin/Pad Function 144-Pin TQFP 1 208-Pin PQFP (1) 240-Pin PQFP (1) 144-Pin 324-Pin 356-Pin FineLine BGA FineLine BGA BGA 1 2 3 4 5 6 7 8 9 10 11 12 13 – –

D4136

Abstract: m 208 b1 PQFP ALTERA 160 EPM7256A EPM7256AE EPM7256E EPM7256S EPM7512AE m64196 L6M15
Contextual Info: EPM7256A and EPM7256AE Dedicated Pin-Outs ver. 1.0 Dedicated Pin 100-Pin TQFP 100-Pin FineLine BGA INPUT/GCLK1 87 A6 INPUT/GCLRn 89 B5 INPUT/OE1 88 B6 INPUT/OE2/GCLK2 90 A5 TDI 1 4 A1 TMS (1) 15 F3 TCK (1) 62 F8 TDO (1) 73 A10 GNDINT 38, 86 D6, G5 144-Pin TQFP 208-Pin PQFP 256-Pin FineLine BGA

337 BGA

Abstract: AA23 AC25 EP20K160E
Contextual Info: EP20K160E I/O Pins ver. 1.2 I/O & VREF Bank 8 8 8 8 – – 8 8 8 8 8 – 8 8 8 8 8 – 8 8 8 8 8 – 8 8 8 8 8 – 8 8 8 8 8 – 8 8 8 8 8 – 8 8 8 8 8 Pad Number Orientation Pin/Pad Function 144-Pin TQFP 208-Pin PQFP 240-Pin PQFP 356-Pin BGA 1 (1) (1)

PQFP ALTERA 160

Abstract: TQFP 132 PACKAGE EPM7256A EPM7256AE EPM7256B EPM7256S EPM7512AE EPM7512B
Contextual Info: EPM7256B Dedicated Pin-Outs ver. 1.1 Dedicated Pin 100-Pin TQFP 144-Pin TQFP 169-Pin Ultra FineLine BGA INPUT/GCLK1 87 125 D8 INPUT/GCLRn 89 127 D6 INPUT/OE1 88 126 D7 INPUT/OE2/GCLK2 90 128 E7 TDI 2 TMS (2) TCK (2) TDO (2) VREFA (3) VREFB (3) GNDINT GNDIO (3)

8-Input AND Gate

Contextual Info: SN5430, SN54LS30, SN54S30 SN7430, SN74LS30, SN74S30 8-INPUT POSITIVE-NAND GATES SDLS099 – DECEMBER 1983 – REVISED MARCH 1988 Copyright  1988, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments

GS8170D36B-333

Abstract: 8170D18 GS8170D36B-300
Contextual Info: Preliminary GS8170D18/36B-333/300/250 209-Bump BGA Commercial Temp Industrial Temp 18Mb Σ1x2Lp DDR SRAM 1M x 18, 512K x 36 250 - 333 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • Double Data Rate Read and Write mode • JEDEC standard SigmaRAM pinout and package

3256E

Contextual Info: ispLSI 3256E In-System Programmable High Density PLD Functional Block Diagram G3 H0 A0 A1 OR Array A2 A3 ORP ORP • IN-SYSTEM PROGRAMMABLE — 5V In-System Programmable ISP using Lattice ISP or Boundary Scan Test (IEEE 1149.1) Protocol — Increased Manufacturing Yields, Reduced Time-toMarket, and Improved Product Quality

Contextual Info: TIBPAL22V10C, TIBPAL22V10AC, TIBPAL22V10AM HIGH-PERFORMANCE IMPACT  PROGRAMMABLE ARRAY LOGIC CIRCUITS SRPS024 – D2943, OCTOBER 1986 – REVISED MARCH 1992 • • • • • • • • • • Choice of Operating Speeds TIBPAL22V10AC . . . 25 ns Max

Contextual Info: SN5430, SN54LS30, SN54S30 SN7430, SN74LS30, SN74S30 8-INPUT POSITIVE-NAND GATES SDLS099 – DECEMBER 1983 – REVISED MARCH 1988 Copyright  1988, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments

AA10

Abstract: AE10 AF10 AG10 AJ10 AK10 EP20K600C AF31
Contextual Info: EP20K600C I/O Pin-Outs ver. 1.0 I/O & VREF Pad Number Bank Orientation Pin/Pad Function 652-Pin BGA 672-Pin FineLine BGA 1,020-Pin FineLine BGA 1 1 – – 1 1 1 – – 8 8 8 8 – – 8 8 8 8 8 – 8 8 8 8 8 – – 8 8 8 8 8 – 8 8 8 8 8 – – 8 8 8

F33 1067

Abstract: 1010 817 f15 AA10 AM11 AN10 EP20K1500C 837 B34 AM3 940
Contextual Info: EP20K1500C I/O Pin-Outs ver. 1.0 I/O & VREF Bank Pad Number Orientation Pin/Pad Function 652-Pin BGA 1,020-Pin FineLine BGA 1 1 1 – 1 1 1 – – 1 1 1 1 – 8 8 8 8 – – 8 8 8 8 – 8 8 8 8 – – 8 8 8 8 – 8 8 8 8 – – 8 8 8 8 – 1 2 3 4 5 6

AC30

Abstract: AD29 AG29 AG30 AK19
Contextual Info: ispLSI 3448 In-System Programmable High Density PLD Functional Block Diagram J3 J2 J1 . J0 Output Routing Pool ORP H3 Output Routing Pool (ORP) H1 H0 G3 D Q D Q K1 G2 OR Array D Q K2 G1 K3 D Q D Q OR Array Twin GLB G0 D Q . • ispLSI FEATURES: — 5V In-System Programmable (ISP ) Using Lattice

SPRS691C

Abstract: EMIF-16 SPRS691 DDR3 jedec DDR3 jedec JESD79-3C TMS320C6678ACYP SPRS691B 841-Pin tms320c6678cyp 8B16B
Contextual Info: TMS320C6678 Multicore Fixed and Floating-Point Digital Signal Processor Data Manual PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not

003FE

Abstract: 9l reset CY7C0831V CY7C0832V CY7C0851V CY7C0852V KRE 101 2003
Contextual Info: CY7C0851V/CY7C0852V CY7C0831V/CY7C0832V 3.3V 64K/128K x 36 and 128K/256K x 18 Synchronous Dual-Port RAM Features Functional Description • True dual-ported memory cells that allow simultaneous access of the same memory location • Synchronous pipelined operation

74HC595 SMD

Abstract: smd transistor w18 T2D DIODE 46 8 pin SMD ic 2068 smd 1a2 QE r525 QE R519 T04 p6 smd GMC31X7R104K50NT u1g SMD
Contextual Info: LXD9781 BGA Demo Board with FPGAs for RMII-to-MII Conversion Developer Manual January 2001 As of January 15, 2001, this document replaces the Level One document Order Number: 249044-001 LXD9781 BGA Demo Board with FPGAs for RMII-to-MII Conversion User Guide.

Contextual Info: SN74LVC112A DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET www.ti.com SCAS289L – JANUARY 1993 – REVISED AUGUST 2005 FEATURES • • • • • • • D, DB, DGV, NS, OR PW PACKAGE TOP VIEW Operates From 1.65 V to 3.6 V Inputs Accept Voltages to 5.5 V

PCI1251B

Contextual Info: PCI1251B GFN/GJG PC CARD CONTROLLER SCPS043A – OCTOBER 1998 D D D D D D D D D D D D D D D D D PCI Power Management 1.0 Compliant ACPI 1.0 Compliant Packaged in GFN 256-Pin BGA or GJG MicroStar BGA PCI Local Bus Specification Revision 2.2 Compliant 1997 PC Card Standard Compliant

74HC109

Contextual Info: [ /Title CD74H C109, CD74H CT109 /Subject (Dual JK FlipFlop with Set and Reset CD54/74HC109, CD54/74HCT109 Data sheet acquired from Harris Semiconductor SCHS140A Dual J-K Flip-Flop with Set and Reset Positive-Edge Trigger March 1998 - Revised May 2000 Features

Contextual Info: SN74HC4066 QUADRUPLE BILATERAL ANALOG SWITCH SCLS325C – MARCH 1996 – REVISED SEPTEMBER 2000 D D D D D D D, DB, N, OR PW PACKAGE TOP VIEW High Degree of Linearity High On-Off Output Voltage Ratio Low Crosstalk Between Switches Low On-State Impedance . . . 50-Ω TYP

HC4024

Contextual Info: [ /Title CD74 HC402 4, CD74 HCT40 24 /Subject (High Speed CMOS CD54/74HC4024, CD54/74HCT4024 Data sheet acquired from Harris Semiconductor SCHS202A High Speed CMOS Logic 7-Stage Binary Ripple Counter November 1997 - Revised May 2000 Features Description

notes on window type air conditioner

Abstract: ISL5217 ISL5239 ISL5239EVAL1 ISL5239KI ISL5929 ISL5961
Contextual Info: ISL5239 Data Sheet July 2002 FN8039.1 Pre-Distortion Linearizer Features The ISL5239 Pre-Distortion Linearizer PDL is a full featured component for Power Amplifier (PA) linearization to improve PA power efficiency and reduce PA cost. • Output Sample Rates Up to 125MSPS

CS466

Abstract: AT91M42800-33AI
Contextual Info: Features • Utilizes the ARM7TDMI ARM Thumb® Processor Core • • • • • • • • • • • • • • • • – High-performance 32-bit RISC Architecture – High-density 16-bit Instruction Set – Leader in MIPS/Watt – Embedded ICE In-circuit Emulation

5384VA

Abstract: AF14 EL B17
Contextual Info: ispLSI 5384V In-System Programmable 3.3V SuperWIDE High Density PLD — Productivity Enhancing Timing Analyzer, Explore Tools, Timing Simulator and ispANALYZER™ — PC and UNIX Platforms Features • SuperWIDE HIGH DENSITY IN-SYSTEM PROGRAMMABLE LOGIC

sad6

Abstract: PCI2050BPDV
Contextual Info: PCI2050B PCIĆtoĆPCI Bridge Data Manual October 2005 Connectivity Solutions SCPS076F IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries TI reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue