20WMB Search Results

74HC

Abstract: 7C344 CY7C344 CY7C344B LTAC01
Contextual Info: CY7C344 CY7C344B i f CYPRESS 32-Macrocell MAX EPLD Features Functional Description • High-performance, high-density re­ placement for TTL, 74HC, and cus­ tom logic • 32 macrocells, 64 expander product terms in one LAB • 8 dedicated inputs, 16 I/O pins

Contextual Info: CY7C344 CY7C344B y CYPRESS 32-Macrocell MAX EPLD Features Functional Description • High-performance, high-density re­ placement for TTL, 74HC, and cus­ tom logic • 32 macrocells, 64 expander product terms in one LAB • 8 dedicated inputs, 16 I/O pins

Contextual Info: PLDC20G10B/PLDC20G10 CMOS Generic 24-Pin Reprogrammable Logic Device Generic architecture to replace stan­ dard logic functions including: 20L10, 20L8,20R8,20R6,20R4,12L10,14L8, 16L6,18L4,20L2, and 20V8 Eight product term s and one OE product term per output

74HC

Abstract: 7C344 CY7C344 CY7C344B 20C02 DD131
Contextual Info: CY7C344 CY7C344B *0 CYPRESS 32-Macrocell MAX EPLD Features Functional Description • High-performance, high-density re­ placement for TTL, 74HC, and cus­ tom logic • 32 macrocells, 64 expander product terms in one LAB • 8 dedicated inputs, 16 I/O pins

C344

Abstract: 10HC 74HC 7C344 CY7C344 CY7C344B 7C344-25 TEA16
Contextual Info: fax id: 6101 1CY 7C34 4B CY7C344 CY7C344B 32-Macrocell MAX EPLD Features sents the densest EPLD of this size. Eight dedicated inputs and 16 bidirectional I/O pins communicate to one logic array block. In the CY7C344 LAB there are 32 macrocells and 64 expander product terms. When an I/O macrocell is used as an

74HC

Abstract: CY7C344 CY7C344B
Contextual Info: CY7C344 CY7C344B CYPRESS 32-Macrocell MAX EPLD Features Functional Description • High-performance, high-density re­ placement for TTL, 74HC, and cus­ tom logic • 32 macrocells, 64 expander product terms in one LAB • 8 dedicated inputs, 16 I/O pins

palc22v10b-15dmb

Abstract: PALC22V10B PALC22V10B-15KMB PALC22V10B-20DMB 22V10B palc22v10b20dmb palc22v10b15kmb palc22v10b-15hc PALC22V10B-15PC palc22v10b15dmb
Contextual Info: PALC22V10B CYPRESS SEMICONDUCTOR — “15” and “20* military 10/15 ns tc o 10/17 ns ts 15/20 ns tpo 50/31 MHz • Advanced second generation PAL ar­ chitecture • Low power — 90 mA max. standard — 100 mA max. military Functional Description The Cypress PALC22V10B is a CMOS se­

CY7C332-25HMB

Abstract: L9646 c3328 L9806 l9634 L9680 L480 L9622 L9626 L9823
Contextual Info: CY7C332 '0 C Y P R E S S F e a tu re s • 12 I/O macrocells each having: — Registered, latched, or transparent array input — A choice of two clock sources — Global or local output enable OE — Up to 19 product terms (PTs) per output — Product terra (PT) output polarity

cy7c344b-25hmb

Abstract: 10HC 74HC 7C344 C344 CY7C344 CY7C344B
Contextual Info: fax id: 6101 1CY 7C34 4B CY7C344 CY7C344B 32-Macrocell MAX EPLD Features sents the densest EPLD of this size. Eight dedicated inputs and 16 bidirectional I/O pins communicate to one logic array block. In the CY7C344 LAB there are 32 macrocells and 64 expander product terms. When an I/O macrocell is used as an

7c344

Abstract: 74HC CY7C344 CY7C344B W1220
Contextual Info: CY7C344 CY7C344B y CYPRESS 32-Macrocell MAX EPLD Features Functional Description • High-performance, high-density re­ placement for TTL, 74HC, and cus­ tom logic • 32 macrocells, 64 expander product terms in one LAB • 8 dedicated inputs, 16 I/O pins

Contextual Info: s rs 'w CY7C332 ~ •• = Registered Combinatorial EPLD CYPRESS — SEMICONDUCTOR Features • 12 I/O macrocells each having: — Registered, latched, or transparent array input — A choice of two clock sources — Global or local output enable OE — Up to 19 product terms (PTs) per

Contextual Info: PLDC18G8 I CYPRESS SEMICONDUCTOR • Fast — Commercial: tpo = 12 ns, tc o = 10 ns, t§ = 10 ns — Military/Industrial: tpD = 15 ns, t c o = 12 ns, t§ — 12 ns • Low power Generic architecture to replace stan­ dard logic functions including: 10H8, 1 2 H 6 ,1 4 H 4 ,16H 2,10L 8,12L 6,14L 4,

L9680

Abstract: L9646
Contextual Info: CY7C332 S r CYPRESS Features Registered Combinatorial EPLD Functional Description 13 input macrocells, each having: — Complementary input — Register, latch, or transparent access — Ttoo clock sources 15 ns tpo max. Low power — 120 mA typical Ice quiescent