1S TI MAP Search Results

Contextual Info: lie Rechte vorbehalten/ HU rights rts m ti 5 4 2 3 1 C 4,85 III B o *> COVER 2 Detail. Dot. Name 30-A U G -00 A ls p a c e loop. 60 13 020 5200 Part-No. 0,50 to 0,65 cable insulator 0 Stand. 27941 Mod. 3 0 - A U G - 0 0 A 1s p a c e Dot. Name HART 1NG EURL

bq8020

Abstract: bq8024 bq80 bq2084 data flash 0x2673 bq2084DBT bq20z80DBT seal BQ2084 BQ802 unseal BQ2084
Contextual Info: Application Report SLUA325 – November 2005 Feature Set Comparison Between bq2084 and bq20z80 Garry Elder . PMP Portable Power ABSTRACT The bq20z80 differs from the bq2084 in several areas, although all bq2084 features are

sn74als164a texas

Contextual Info: SN74ALS164A 8-BIT PARALLEL-OUT SERIAL SHIFT REGISTER SDAS159D – APRIL 1982 – REVISED DECEMBER 1994 • • • • D OR N PACKAGE TOP VIEW AND-Gated ( Enable/Disable) Serial Inputs Fully Buffered Clock and Serial Inputs Direct Clear Package Options Include Plastic

Contextual Info: SN74ALS164A 8-BIT PARALLEL-OUT SERIAL SHIFT REGISTER SDAS159D – APRIL 1982 – REVISED DECEMBER 1994 • • • • D OR N PACKAGE TOP VIEW AND-Gated ( Enable/Disable) Serial Inputs Fully Buffered Clock and Serial Inputs Direct Clear Package Options Include Plastic

1s Ti MAP

Contextual Info: SN74ALS166 PARALLEL-LOAD 8-BIT SHIFT REGISTER SDAS156D – APRIL 1982 – REVISED AUGUST 2000 D D D D Synchronous Load Direct Overriding Clear Parallel-to-Serial Conversion Package Options Include Plastic Small-Outline D and Shrink Small-Outline (DB) Packages and Standard Plastic (N) DIP

Contextual Info: SN74ALS166 PARALLEL-LOAD 8-BIT SHIFT REGISTER SDAS156D – APRIL 1982 – REVISED AUGUST 2000 D D D D Synchronous Load Direct Overriding Clear Parallel-to-Serial Conversion Package Options Include Plastic Small-Outline D and Shrink Small-Outline (DB) Packages and Standard Plastic (N) DIP

Contextual Info: SN54HC590A, SN74HC590A 8ĆBIT BINARY COUNTERS WITH 3ĆSTATE OUTPUT REGISTERS SCLS039F − DECEMBER 1982 − REVISED SEPTEMBER 2003 D 2-V to 6-V VCC Operation D High-Current 3-State Parallel Register Outputs Can Drive Up To 15 LSTTL Loads D Low Power Consumption, 80-µA Max ICC

8051 interfacing to EProm

Abstract: intel 8051 architecture intel 8098 290165
Contextual Info: INTEL CORP UP/PRPHLS 12E D MflEt.175 O O b lS Q ? i^ÊÉruÜi. T ' 5 2 - 3 3 -O S 87C75PF MICROCONTROLLER PERIPHERAL I/O PORT EXPANDER WITH 32Kx8 EPROM No^Glue Microcontroller Interface — Programmable Memory Map — Programmable Control Signals -. — Built-in Address Latches

Contextual Info: SN74AS298A QUADRUPLE 2-INPUT MULTIPLEXER WITH STORAGE SDAS219B – DECEMBER 1983 – REVISED DECEMBER 1994 • • • D OR N PACKAGE TOP VIEW Selects One of Two 4-Bit Data Sources and Synchronously Stores Data With System Clock Applications: – Dual Source for Operands and Constants

Contextual Info: SN74AS298A QUADRUPLE 2-INPUT MULTIPLEXER WITH STORAGE SDAS219B – DECEMBER 1983 – REVISED DECEMBER 1994 • • • D OR N PACKAGE TOP VIEW Selects One of Two 4-Bit Data Sources and Synchronously Stores Data With System Clock Applications: – Dual Source for Operands and Constants

N8T24

Contextual Info: SN75124 TRIPLE LINE RECEIVER SLLS058B – SEPTEMBER 1973 – REVISED MAY 1995 D D D D D D D D D D OR N PACKAGE TOP VIEW Meets or Exceeds the Requirements of IBM System 360 Input/Output Interface Specification Operates From Single 5-V Supply TTL Compatible

special function registers of intel 8096 microcontroller

Abstract: 8096 microcontroller block diagram ci402 8051 interfacing to EProm intel 8098 290165 8096 microcontroller architecture 8096 microcontroller architecture application 8096 microcontroller features CEC P0o
Contextual Info: INTEL CORP UP/PRPHLS 2QE D • 4fl2t.l?S O D V T H ? ? P iiy K In te l 87C75PF MICROCONTROLLER PERIPHERAL I/O PORT EXPANDER WITH 32Kx8 EPROM G ■ Ä « ? T-52-33-Off No-Glue Microcontroller Interface — Programmable Memory Map — Programmable Control Signals

80C51

Abstract: transistor s6p
Contextual Info: Phlips Semiconductors 80C51 Family 80C51 family hardware description • The Serial Interface • The Interrupt System • Reset • The Reduced Power Modes in CMOS devices • The EPROM version of the 80C51 HARDWARE DESCRIPTION This chapter provides a detailed description of the 80C51

FET pair n-channel p-channel

Abstract: crystal 11.059MHZ datasheet of tcon register of 8051 8048 microcontroller APPLICATION depletion mode fet TI 8048 CPU ET10 transistor 5-phase HD7417P interfacing 8051 with eprom and ram
Contextual Info: Phlips Semiconductors 80C51 Family 80C51 family hardware description • The Serial Interface • The Interrupt System • Reset • The Reduced Power Modes in CMOS devices • The EPROM version of the 80C51 HARDWARE DESCRIPTION This chapter provides a detailed description of the 80C51

IC80C51

Abstract: MC001-0B
Contextual Info: IC80C51 IC80C31 IC80C51 IC80C31 CMOS SINGLE CHIP 8-BIT MICROCONTROLLER FEATURES GENERAL DESCRIPTION • • • • • • • • The ICSI IC80C51 and IC80C31 are high-performance microcontroller fabricated using high-density CMOS technology. The CMOS IC80C51/31 is functionally

la 78141 equivalent

Abstract: LA 78141 data tech 12512 clover high tech TIBPAL22VP10-20C
Contextual Info: TIBPAL22VP10-20C, TIBPAL22VP10-25M HIGH-PERFORMANCE IMPACT-X  PROGRAMMABLE ARRAY LOGIC CIRCUITS SRPS013 – D2943, FEBRUARY 1987 – REVISED JUNE 1991 • • • • • • • • CLK/I I I I I I I I I I I GND Choice of Operating Speeds: TIBPAL22VP10-20C . . . 20 ns Max

MC001-0B

Abstract: IS80C31
Contextual Info: IS80C51 IS80C31 IS80C51 IS80C31 CMOS SINGLE CHIP 8-BIT MICROCONTROLLER FEATURES • • • • • • • • • • • • • • • 80C51 based architecture 4K x 8 ROM IS80C51 only 128 x 8 RAM Two 16-bit Timer/Counters Full duplex serial channel

at89c52 base clock

Abstract: at89c52 base clock circuit diagram AT89C52 TIMER0 AT89C2051 microcontroller interrupt counting code at89c52 base clock circuit AT89C51 Interrupt Priority AT89C51 hardware interfacing at89c52 full instruction set introduction to microcontroller AT89C52 at89c52 base clock circuit diagram free
Contextual Info: Introduction This chapter presents a comprehensive description of the on-chip hardware features of Atmel’s Flash-based microcontrollers. Included in this description are the following items. • The port drivers and how they function both as ports and, for Ports 0 and 2, in bus

11.059mHz crystal oscillator

Abstract: 80C51 80C51 family hardware
Contextual Info: Phlips Semiconductors 80C51 Family 80C51 family hardware description • The Serial Interface • The Interrupt System • Reset • The Reduced Power Modes in CMOS devices • The EPROM version of the 80C51 HARDWARE DESCRIPTION This chapter provides a detailed description of the 80C51

IC 74HC112

Abstract: HC112
Contextual Info: [ /Title CD74 HC112 , CD74 HCT11 2 /Subject (Dual J-K FlipFlop with Set and Reset Nega- CD54/74HC112, CD54/74HCT112 Data sheet acquired from Harris Semiconductor SCHS141B Dual J-K Flip-Flop with Set and Reset Negative-Edge Trigger March 1998 - Revised March 2002

AT8952

Abstract: at89c52 base clock circuit diagram at89c52 base clock circuit diagram free at89c52 base clock Microcontroller AT89C2051 instruction set AT89C51 hardware interfacing AT89C51 INSTRUCTIONS SET at89c52 base clock circuit at89 programmer MICROCONTROLLER AT89C51 pin diagram
Contextual Info: AT89 Series Hardware Description Introduction This chapter presents a comprehensive description of the on-chip hardware features of Atmel’s Flash-based microcontrollers. Included in this description are the following items. • The port drivers and how they function both as ports and, for Ports 0 and 2,

80C51

Abstract: IS80LV31 IS80LV51 mc018
Contextual Info: IS80LV51 IS80LV31 IS80LV51 IS80LV31 ISSI ISSI CMOS SINGLE CHIP LOW VOLTAGE 8-BIT MICROCONTROLLER ® ADVANCE INFORMATION OCTOBER 1998 FEATURES GENERAL DESCRIPTION • • • • • • • • The ISSI IS80LV51 and IS80LV31 are high-performance microcontrollers fabricated using high-density CMOS

IS80C31

Abstract: 80C51 IS80C51
Contextual Info: IS80C51 IS80C31 IS80C51 IS80C31 ISSI ISSI CMOS SINGLE CHIP 8-BIT MICROCONTROLLER ® NOVEMBER 1998 FEATURES GENERAL DESCRIPTION • • • • • • • • The ISSI IS80C51 and IS80C31 are high-performance microcontrollers fabricated using high-density CMOS

80C51

Abstract: 80C52 IS89C51
Contextual Info: ISSI ISSI IS89C51 IS89C51 CMOS SINGLE CHIP 8-BIT MICROCONTROLLER with 4-Kbytes of FLASH ® PRELIMINARY MAY 1998 FEATURES GENERAL DESCRIPTION • 80C51 based architecture • 4-Kbytes of on-chip Reprogrammable Flash Memory • 128 x 8 RAM • Two 16-bit Timer/Counters