199S Search Results

Contextual Info: SN74LVC16543 16-BIT REGISTERED TRANSCEIVER WITH 3-STATE OUTPUTS 3CAS317A- NOVEMBER 1993 - REVISED OCTOBER 199S | • Member of the Texas Instruments Wldobua Family • EP/C™ Enhanced-Performance Implanted CMOS Submicron Process • Typical V q l p (Output Ground Bounce)

TL14310

Abstract: TL1431C SLVS062B
Contextual Info: TL1431C, TL1431Q, TL1431Y PRECISION PROGRAMMABLE REFERENCES SLVS062B - DECEMBER 1991 - REVISED AUGUST 199S D PACKAGE TOP VIEW 0.4% Initial Voltage Tolerance 0.1-Q Typical Output Impedance Fast Turn O n . . . 500 ns Sink Current Capability. . . 1 mA to 100 mA

44460D

Abstract: BK36C-80
Contextual Info: TM124MBK36C, TM124MBK36S1048576 BY 36-BIT TM248NBK36C, TM248NBK36S 2097152 BY 36-BIT DYNAMIC RAM MODULE SMMS138B - MARCH 1992 - REVISED JUNE 199S Enhanced Page Mode Operation With CAS-Before-RAS CBR , RAS-Only, and Hidden Refresh Presence Detect Performance Ranges:

Contextual Info: SN54AC74, SN74AC74 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET _SCASS21C- AUGUST 199S - REVISED SEPTEMBER 1996 EPIC Enhanced-Performance Implanted CMOS 1-|im Process SN54AC74 . . . J OR W PACKAGE SN74AC74 . . . D, DB, N, OR PW PACKAGE

SN74ACTOO

Contextual Info: SN54ACT00, SN74ACT00 QUADRUPLE 2-INPUT POSITIVE-NAND GATES S C A S 5 2 3 A -AU G U S T 199S - R E V IS E D MAY 1996 Inputs Are TTL-Voltage Compatible EPIC Enhanced-Performance Implanted CMOS 1-ixm Process Package Options Include Plastic Small-Outllne (D), Shrink Small-Outllne

transformer EP10

Abstract: HI-POT 0516
Contextual Info: RoHS EP10 POWER TRANSFORMER AEP-199SI EP10 Transformer Design SMT Operating Temperature: -40ºC to 85ºC Pulse PA1370NL Part Number Turns Ratio @10KHz,0.1V 3-4:5-8:2-1 Ungapped Core AEP-199SI 1:0.44:0.39±2% Inductance @10KHz,0.1V DCR @25° C 3-4 3-4 20.4µH±8%

NTC SD-9

Abstract: R1561 NTC SD-15 PLS4148 S72I MUAB
Contextual Info: 199SlSh< — SSVnSSSWS — — T T- 3 3 9 333 3333333333 3 3 333333333 la o rfN P K A V M ia 5 Q Ö Ö O O Ö Ö f l Hr'p,^'‘rtrt^ HrtNfHiN«NNN«NNrtnrtf»nnnonrt'»*-i’f>»i»*f •»¥í'iflíi«fiirtioiíiinifiift'í'í'íií K i n i i h a f t O '-

Contextual Info: SN54AS821A, SN74AS821A 10-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS SDAS230A- DECEMBER 1983 - REVISED AUGUST 199S Functionally Equivalent to AMD's AM29821 Provide Extra Data Width Necessary for Wider Address/Data Paths or Buses With Parity SN54AS821A . . . JT PACKAGE

2sa11

Contextual Info: h ~7y y 7 $ /T ra n s is to rs 2SA 119 9 /2 S A 1 199S 2SA1199 199S 7’ JU-Jls-J-BPNP S ÿ > y 7,$ Epitaxial Planar PNP Silicon Transistors & 7 'f y ? y y^ffl/Medium Power Amp. & Switching • H i f i T fä E l/'D im e n s io n s U nit : mm 1) VcE(sat) &&

V143Y

Abstract: SN74AS1805
Contextual Info: SN74AS1805 HEX 2-INPUT NOR DRIVER SDAS043C - AUGUST 1964 - REVISED JANUARY 199S • High Capacltlve-Drlve Capability • Typical Delay Time of 2.6 ns CL = 50 pF and typical Power Dissipation of Less Than 12 mW Per Qate • Center V cc and GND Configuration

Contextual Info: TLC548C, TLC548I, TLC549C, TLC549I 8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL SLAS067A- NOVEMBER 1983 - REVISED MARCH 199S • Microprocessor Peripheral or Stand-Alone Operation • 8-Bit Resolution A/D Converter D OR P PACKAGE TOP VIEW REF+

Contextual Info: SN74CBT3384A 10-BIT BUS SWITCH I SCDS004C - NOVEMBER 1992 - REVISED JULY 199S ! DB, DW, OR PW PACKAQE TOP VIEW • Functionally Equivalent to QS3384 and QS3L384 • 5-£2 Switch Connection Between Two Ports • TTL-Compatlble Input and Output Levels • Package Options Include Plastic Shrink

74LVC138

Contextual Info: SN74LVC138 3-LINE TO 8-LINE DECODER/DEMULTIPLEXER SCAS291B - MARCH 1993 - REVISED JULY 199S • EP/C Enhanced-Performance Implanted CMOS Submicron Process • ESD Protection Exceeds 2000 V Per MIL-STD-883C, Method 3015; Exceeds 200 V Using Machine Model

u860

Abstract: TM497GU8
Contextual Info: TM497GU8 4194304-WORD BY 8-BIT DYNAMIC RAM MODULE SMMS49BA-APRIL 1 9 9 4 - REVISED JUNE 199S • Organization . . . 4194304 x 8 I U SINGLE-IN-LINE PACKAGE • Single 5-V Power Supply ±10% Tolerance • 30-Pln Slngle-ln-Llne Memory Module (SIMM) for Use With Sockets

27C510

Abstract: 27c810-17 27C810
Contextual Info: TMS27C510 524288-BIT UV ERASABLE PROGRAMMABLE TMS27PC510 524288-BIT PROGRAMMABLE READ-ONLY MEMORY SMLS51 O B-A U G U S T 1990 - REVISED JUNE 199S • Organization . . . 64K x 8 • Single 5-V Power Supply • Pin Compatible With Existing 1 Meg MOS ROMs, PROMs, and EPROMs

lta21

Contextual Info: SN74LVC541 OCTAL BUFFER/DRIVER WITH 3-STATE OUTPUTS S C A S 2 9 8 B -J A N U A R Y 1 9 9 3 - REVISED JULY 199S OB, DW, OR PW PACKAGE TOP VIEW EP/C (Enhanced-Performance Implanted CMOS) Submicron Process Typical V q l p (Output Ground Bounce) < 0.8 V at Vc c = 3.3 V, TA = 25°C

Contextual Info: ISI/CSI □□□ LS7266 □□□ Since 1969 LSI Computer Systems, Inc. 1235 UJolt Whitman Road, Melville, NV 11747 516 271-0400 FAX (516) 271-0405 24-BIT DUAL-AXIS QUADRATURE COUNTER March 199S PIN ASSIGNMENT - TOP VIEW Standard 28-Pin Plastic DIP FEATURES:

Contextual Info: ISI/CSI • B l ■ ■ ■ = ■ LS7083/7084 Since 1969 LSI Computer Systems, Inc. 1235 UJcilt Whitman Rood, Melville, NV 11747 516 271-0400 FAX (516) 271-0405 A p ril 199S QUADRATURE CLOCK CONVERTER FEATURES: • X1 and X4 mode selection • Up to 16 MHz output clock frequency

lt1084v

Contextual Info: LT1004C-1.2, LT1004C-2.5, LT1004M-1.2 LT1004M-2.5, LT1004Y-1.2, LT1004Y.2.5 MICROPOWER INTEGRATED VOLTAGE REFERENCES SLVS022D - JANUARY 1989 - REVISED AUGUST 199S Initial Accuracy ±4 mV for LT1004-1.2 ±20 mV for LT1004-2.5 Micropower Operation Operates up to 20 mA

BH RU

Contextual Info: TMS626802 1048576-WORD BY 8-BIT BY 2-BANK SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORY SMOS162A - FEBRUARY 1994 - REVISED JUNE 199S Organization . . . 1M x 8 x 2 Banks 3.3-V Power Supply ±10% Tolerance Two Banks for On-Chip Interleaving (Gapless Accesses) High Bandwidth - Up to 100-MHz Data

Contextual Info: SN54AC32, SN74AC32 QUADRUPLE 2-INPUT POSITIVE-OR GATES SCAS528B - AUGUST 199S - REVISED SEPTEMBER 1996 SN54AC32 . . . J OR W PACKAGE SN74AC32 . . . D, DB, N, OR PW PACKAGE TOP VIEW EPIC (Enhanced-Performance Implanted CMOS) 1-|im Process Package Options Include Plastic

SN74LVC244A

Contextual Info: SN74LVC244A OCTAL BUFFER/DRIVER WITH 3-STATE OUTPUTS I SCAS414C - NOVEMBER 1992 - REVISED JULY 199S DB, DW, OR PW PACKAGE TOP VIEW EPIC (Enhanced-Performance Implanted CMOS) Submicron Process Typical V q l p (Output Ground Bounce) < 0.8 V at Vc c = 3.3 V, TA = 25°C

Contextual Info: CDC2536 3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS SCAS377B - APRIL 1994 - REVISED NOVEMBER 199S Operates at 3.3-V Vcc Distributes One Clock Input to Six Outputs One Select Input Configures Three Outputs to Operate at One-Half or Double the Input

Contextual Info: 4 THIS DRAWING IS UNPUBLISHED. M. COPYRIGHT 199S RELEASED FOR PUBLICATION BTTT , 1996 REVISIONS BY AHP INCORPORATED.ALL RIGHTS RESERVED. U th L D I RE CT IO N OFF TOP OF REEL 3E IK ECN DATE DUN APVD RELEASED F J O O - 4738-96 6 / J U N / '96 T. K Y. Y REVISED