18 PIN STATIC RAM Search Results

Contextual Info: «O V i C 1992 MEC il PD431018 65,536 x 18-Bit Static CMOS RAM NEC Electronics Inc. Preliminary Information October 1992 Description Pin Configurations The /1/PD431018 is a 65,536-word by 18-bit static RAM fabricated with advanced silicon-gate technology,

Contextual Info: SE C NEC Electronics Inc. fiPD431018 65,536 X 18-Bit Static CMOS RAM Description Pin Configurations The ¿¿PD431018 is a 65,536-word by 18-bit static RAM fabricated with advanced silicon-gate technology, unique CMOS peripheral circuits, and N-channel mem­

118-TP

Contextual Info: MITSUBISHI LS Is , M5M5V1B118TP,RT-8,-10,-12 1179648-BIT 65536-WORD BY 18-BIT BiCMOS SYNCHRONOUS STATIC RAM DESCRIPTION The M 5 M 5V 1B 118 is a fam ily o f 6 5 536-w ord by 18-bit synchronous static R A M s, fabricated w ith the PIN CONFIGURATION (TOP VIEW)

4804B

Abstract: 4804 4804BCC semi 4804 4804a c 4804a TCO 706 1N3064 EMM Semi
Contextual Info: GENERAL DESCRIPTION FEATURES • Single +5V Power Supply ■ 1Kx4 Organization ■ Replaces 41024x1 Static RAMs ■ Completely Static—No Clocks or Refresh ■ 18 Pin Package ■ Access/Cycle Times As Low As 400 nsec max ■ 250 mw Typical Operating Power

M2114A

Abstract: M2148H 1kx4 n irc 1028
Contextual Info: intei M2148H HIGH SPEED 1024 x 4 BIT STATIC RAM MILITARY M2148H 70 Max. Access Time ns 180 Max. Active Current (mA) 30 Max. Standby Current (mA) HMOS E Technology High Density 18-Pin Package Completely Static Memory- •No Clock or Timing Strobe Required

Contextual Info: MITSUBISHI LS Is t jw ^ M 5 M 5 V 1 B 0 1 8 J ,T P ,R T - 1 0 ,-1 2 ,-1 5 1179648-BIT 65536-WORD BY 18-BIT BICMOS STATIC RAM DESCRIPTION The M5M5V1B018 is a family of 65536-word by 18-bit PIN CONFIGURATION (TOP VIEW) static RAMs, fabricated with the high performance BiCMOS

IC 4804

Contextual Info: FEATURES • Single +5V Power Supply ■ 1Kx4 Organization ■ Replaces 41024x1 Static RAMs ■ Completely Static—No Clocks or Refresh ■ 18 Pin Package ■ Access/Cycle Times As Low As 400 nsec max ■ 250 mw Typical Operating Power ■ Common I/O Bus

M2147

Abstract: intel 2147
Contextual Info: in te i M2147 4096 X 1 BIT STATIC RAM M2147 Max. Access Time ns 85 180 Max. Active Current (mA) Max. Standby Current (mA) 30 HMOS Technology Automatic Power-Down Completely Static Memory — No Clock or Timing Strobe Required High Density 18-Pin Package

82385

Abstract: micron memory sram cache micron memory sram intel 82385 74LS373 A12 marking intel sram MT56C0416 1638C 1.2 Micron CMOS Process Family
Contextual Info: ADVANCE M IC R O N MT56C0416 DUAL 4Kx 16/18 SRAM, SINGLE 8Kx 16/18 CACHE DATA STATIC RAMS CO NFIGURABLE CACHE DATA RAM FEATURES PIN A SS IG N M E N T Top View • Operates as two 4K x 16/18 SRAMs with common addresses, common data and separate control signals.

5114 ram

Abstract: 5114 intel 2114a 2114a
Contextual Info: 5114 1024 x 4 BIT STATIC CM O S RAM • Fully Static Operation; No Clocks, Strobes or Latches ■ Data Retention at 2.0V ■ Identical Cycle and Access Times ■ High Performance; 150 ris Access Time ■ TTL Compatible Inputs and Outputs ■ Hi9 h Dens'ty 18-Pin Package

Contextual Info: 3ÔE D MICRON TECHNOLOGY INC blllSM'l QGQ3G2Q 1 • MRN r - % - n - ìz aìa r CACHE DATA STATIC RAM DUAL 4Kx 18 SRAM, SINGLE 8Kx 18 SRAM CONFIGURABLE CACHE DATA SRAM FEATURES PIN ASSIG N M EN T Top View • Automatic WRITE cycle completion • Operates as two 4K x 18 SRAMs with common

MK2147-70

Abstract: MK2147-55 vs5-24v MK2147 MK2147-85
Contextual Info: MOSTEK 4K x 1 -BIT STATIC RAM M K 2147 J -55/70/85 FEATURES □ Address Activated static m em ory— no clock or tim in g strobe required □ Sicaled Poly 5™ technology □ Industry standard 18-pin dip configuration □ Access tim e equal cycle tim e

Contextual Info: intei M2148H HIGH SPEED 1024 x 4 BIT STATIC RAM Military M2148H-3 M2148H Max. Access Time ns 55 70 Max. Active Current (mA) 180 180 Max. Standby Current (mA) 30 30 H M O S III Technology High Density 18-Pin Package Completely Static Memory — No Clock or Timing Strobe Required

5104

Abstract: N5104 2141 ram 2141 intel 5104 dm
Contextual Info: A[WM1 I 0MF© GM¥0®M intéf 5104 4096 x 1 BIT STATIC CMOS RAM • Data Retention at 2.0V Fully Static Operation; No Clocks, Strobes or Latches High Performance; 150 ns Access Time ■ Identical Cycle and Access Times TTL Compatible Inputs and Outputs ■ High Density 18-Pin Package

K 3567

Contextual Info: 06/18/% 09:52:57 40B-49Z-B6?4-> 16038801932 IDT CMOS STATIC RAM 256K 32K x 8-BIT Page 002 IDT71256SA70 Integrated Device Technology, Inc. FEATURES: DESCRIPTION: • 32K x 8 C M O S static RAM • Equal access and cycle times - Commercial: 70ns • O n e Chip Select plus one Output Enable pin

diagram block ram 16 4bit

Abstract: 18 pin static ram
Contextual Info: M O T O R O L /L PRODUCT PREVIEW CMOS LSI LOW PO W ER C O M PL E M E N T A R Y M OS IK x 4 STATIC RAM 1 K x 4 STATIC RAM • • • • 1024 words by 4-Bit Organization. Indsutry Standard 18-pin Configuration. Single Supply — 5 V o lt Operation. Fully Static — No Clocks or Refresh required.

Contextual Info: PRELIMINARY INFORMATION L7C108 L7C109 128K x 8 Static RAM Pin Configuration 32-pin Ceramic DIP 32-pin Ceramic SOJ NC A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ1 DQ2 DQ3 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17

pin diagram of 8355 with timer

Abstract: pin diagram of 8355 8355/8755 intel microprocessor block diagram 8355 rom chip MCS-85 8088 ram intel 8355 ic M8185 8755A intel 8185
Contextual Info: [PlfäliyiMOIMCW intei M8185* 1024 x 8-BIT STATIC RAM FOR MCS-85 ‘ Compatible with 8CI85A. MILITARY Multiplexed Address and Data Bus • Low Standby Power Dissipation Directly Compatible with 8085A and 8088 Microprocessors ■ Single +5V Supply ■ High Density 18-Pin Package

intel 8185

Abstract: pin diagram of 8355 with timer intel 8355 8185 8355 rom chip MCS-85 8155 intel microprocessor block diagram intel 8085A 8355/8755 intel microprocessor block diagram 8085A-2
Contextual Info: inte1 8185/8185-2 1024 x 8-BIT STATIC RAM FOR MCS-85* • Multiplexed Address and Data Bus ■ Low Standby Power Dissipation ■ Directly Compatible with 8085A and iAPX 88 Microprocessors ■ Single +5V Supply ■ Low Operating Power Dissipation ■ High Density 18-Pin Package

Contextual Info: CAT22C10 256-Bit Nonvolatile CMOS Static RAM FEATURES • Single 5V Supply ■ Low CMOS Power Consumption: -A ctive: 40mA Max. -Standby: 30 |iA Max. ■ Fast RAM Access Times: -200ns -300ns ■ JEDEC Standard Pinouts: -18-pln DIP -16-pin SOIC ■ Infinite E2PROM to RAM Recall

Contextual Info: 1K Commercial X2212A 2 5 6 x 4 Bit Nonvolatile Static RAM FEATURES • Single 5V Supply • Fully TTL Compatible • JEDEC Standard 18-Pin Package • Infinite E2PROM Array Recall, RAM Read and Write Cycles • Access Time of 250 ns Max. • Nonvolatile Store Inhibit: Vcc = 3V Typical

40L45

Abstract: 40L47-45 40L47 Telect 18-PIN 40L45-45 40L45-30
Contextual Info: MOS LSI TM S 40L45 JL. NL; TMS 40L47 JL. NI 1024-W QRD BY 4-B IT STATIC RAMi N O V E M B ffl 1177 1024 x 4 Organization Single 10% Tolerance TM S40L46 18-PIN C E R A M IC A N D PL A S TIC D U A L - IN - L IN E P A C K A G E S TOP V IE W 5-V Supply High Density 300-m il 18- and 20-Pin Packages

128K x 8 Static RAM

Abstract: 5962-8959812MYA 5962-8959810MZ
Contextual Info: L7C108 L7C109 128K x 8 Static RAM Pin Configuration     32-pin Ceramic DIP 32-pin Ceramic SOJ NC A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ1 DQ2 DQ3 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC A15 CE2 WE A13

2kx8 EPROM

Contextual Info: 1Kx4 CMOS Static RAM PIN CONFIGURATION UM6116 1 18 □ vcc C 2 17 □ A7 *A 4 C ’3 16 □ A8 A3 C 4 A6 L ab Ao C Ai C A2 C c l E : 5 - • Single 5V Supply and High Density 24 Pin Package ■ High speed: Fast Access Time 55/70/90 ns Max. ■ Low Power Standby and