162511CT Search Results

Contextual Info: Integrated D evice Technology, Inc. FAST CMOS 16-BIT REGISTERED/LATCHED TRANSCEIVER WITH PARITY FEATURES: • • • • • • • • • • • 0.5 MICRON CMOS Technology Typical tsk o (Output Skew) < 250ps, clocked mode Low input and output leakage <1 ixA (max)

Contextual Info: Integrated Device Technology, Inc. FAST CMOS 16-BIT REGISTERED/LATCHED TRANSCEIVER WITH PARITY FEATURES: • • • • • • • • • • • IDT54/74FCT162511AT/CT type latches and D-type flip-flops to allow data flow in transpar­ ent, latched or clocked modes. The device has a parity

Contextual Info: Integrated Device Technology, Inc. FAST CMOS 16-BIT REGISTERED/LATCHED TRANSCEIVER WITH PARITY FEATURES: • • • • • 0 .5 M IC R O N C M O S T e c h n o lo g y T yp ica l tsk o (O u tput S kew ) < 2 5 0 p s , clo cke d m o de L o w in p u t an d o u tp u t leaka ge <1 (iA (m ax)

74fct162511 idt

Contextual Info: FAST CMOS 16-BIT REGISTERED/LATCHED TRANSCEIVER WITH PARITY FEATURES: • • • • • • • • • • • IDT54/74FCT162511 AT/CT PRELIMINARY type latches and D-type flip-flops to allow dataflow in transpar­ ent, latched or clocked modes. The device has a parity

SO56-2

Abstract: phase cheker
Contextual Info: Integrated Device Technology, Inc. FEATURES: • • • • • • • • • • • IDT54/74FCT162511AT/CT FAST CMOS 16-BIT REGISTERED/LATCHED TRANSCEIVER WITH PARITY 0.5 MICRON CMOS Technology Typical tsk o (Output Skew) < 250ps, clocked mode Low input and output leakage ≤1µA (max)

phase cheker

Abstract: B1A16 SO56-2
Contextual Info: Integrated Device Technology, Inc. FEATURES: • • • • • • • • • • • IDT54/74FCT162511AT/CT PRELIMINARY FAST CMOS 16-BIT REGISTERED/LATCHED TRANSCEIVER WITH PARITY 0.5 MICRON CMOS Technology Typical tsk o (Output Skew) < 250ps, clocked mode

u3042

Abstract: R3051 R3052 R3081 R36100 R4640 R4650 13w3 u3078 A7 B14
Contextual Info: Integrated Device Technology, Inc. IDT79S500 Evaluation Board Hardware User’s Manual Version 2.0 February 1998 2975 Stender Way, Santa Clara, California 95054 Telephone: 800 345-7015 • TWX: 910-338-2070 • FAX: (408) 492-8674 Printed in U.S.A. 1998 Integrated Device Technology, Inc.

Contextual Info: Integrated Device Technology, Inc. FAST CMOS 16-BIT REGISTERED/LATCHED TRANSCEIVER WITH PARITY FEATURES: • • • • 0.5 MICRON CM O S Technology Typical tsk o (Output Skew) < 250ps, clocked mode Low input and output leakage <1 jxA (max) ESD > 2000V per M IL-STD-883, Method 3015;

Contextual Info: FAST CMOS 16-BIT REGISTERED/LATCHED TRANSCEIVER WITH PARITY r?y integrated Devi ce Technology, Inc. FEATURES: • • • • IDT54/74FCT162511AT/CT PRELIMINARY ty p e latch es and D -typ e flip -flo p s to a llo w d a ta flo w in tra n s p a r­ ent, latch ed o r clo c k e d m o des. T h e d e v ic e h a s a p a rity

SO56-2

Abstract: phase cheker
Contextual Info: Integrated Device Technology, Inc. FEATURES: • • • • • • • • • • • IDT54/74FCT162511AT/CT FAST CMOS 16-BIT REGISTERED/LATCHED TRANSCEIVER WITH PARITY 0.5 MICRON CMOS Technology Typical tsk o (Output Skew) < 250ps, clocked mode Low input and output leakage ≤1µA (max)

u3078

Abstract: u3042 79S500 R3051 R3052 R3081 R36100 R4650 R4700 c4429
Contextual Info: Integrated Device Technology, Inc. 79S500 Evaluation Board Hardware User’s Manual Version 1.0 Rev. B Board September 1996 2975 Stender Way, Santa Clara, California 95054 Telephone: (800) 345-7015 • TWX: 910-338-2070 • FAX: (408) 492-8674 Printed in U.S.A.

DE-A10

Abstract: SED1345 JS41 TP177 29F400 flash DEA10 act 30b equivalent SOD-17 GALILEO TECHNOLOGY procedure TP61 equivalent
Contextual Info: 64-bit R4XXX Galileo-4 Evaluation & Development Preliminary November 95, Rev. 1.0 System FEATURES • Evaluation, benchmark, software, and hardware development system - R4XXX PCI Controller adapter board - Passive PCI Backplane motherboard - Optional Galileo-2 Secondary Cache module

phase cheker

Abstract: psc2101
Contextual Info: H htegiated D e v iz e T e c h n o lo g y , l i e . FAST CMOS 16-BIT REGISTERED/LATCHED TRANSCEIVER WITH PARITY FEATURES: • • • • • • • • • • • 0.5 MICRON CM O S Technology Typical tsk o (Output Skew) < 250ps, clocked mode Low input and output leakage <1 jxA (max)

phase cheker

Abstract: SO56-2 fct162511ct B1A16
Contextual Info: Integrated Device Technology, Inc. FEATURES: • • • • • • • • • • • IDT54/74FCT162511AT/CT PRELIMINARY FAST CMOS 16-BIT REGISTERED/LATCHED TRANSCEIVER WITH PARITY 0.5 MICRON CMOS Technology Typical tsk o (Output Skew) < 250ps, clocked mode