160AT Search Results

Contextual Info: SIEMENS HYB39S64400/800/160AT L 64MBit Synchronous DRAM 64 MBit Synchronous DRAM • High Performance: Multiple Burst Operation -8 -8B -10 Units fCKmax. 125 100 100 MHz tCK3 8 10 10 ns tAC3 6 6 7 ns Automatic Command and Read with Single Write Controlled

PC100-322-620

Abstract: PC-100-322-620 PC133-333-520 PC100-222-620 P-TSOPII-54 39S256400AT-8A SMD MARKING CODE t15
Contextual Info: HYB 39S256400/800/160AT 256-MBit Synchronous DRAM 256-MBit Synchronous DRAM Preliminary Datasheet • Multiple Burst Read with Single Write Operation • High Performance: • Automatic and Controlled Precharge Command -7.5 -8 -8A -8B Units fCK 133 125 125

TSOP66

Abstract: HYB25D512400
Contextual Info: HYB25D512400/800/160AT L 512-MBit Double Data Rata SDRAM Preliminary Datasheet 2002-03-17 Features CAS Latency and Frequency CAS Latency 2 2.5 Maximum Operating Frequency (MHz) DDR200 DDR266A DDR333 -8 -7 -6 100 133 133 125 143 166 • Double data rate architecture: two data transfers

T10-T12

Abstract: T11-T12 SPT03927
Contextual Info: HYB 39S64400/800/160AT L 64 MBit Synchronous DRAM Timing Diagrams 1 Bank Activate Command Cycle 2 Burst Read Operation 3 Read Interrupted by a Read 4 4.1 4.2 4.3 Read to Write Interval Read to Write Interval Minimum Read to Write Interval Non-Minimum Read to Write Interval

TSOP66

Abstract: HYB25D512400AT DDR200 DDR266A DDR333
Contextual Info: HYB25D512400/800/160AT L 512-MBit Double Data Rata SDRAM Preliminary Datasheet 2002-03-17 Features CAS Latency and Frequency CAS Latency 2 2.5 Maximum Operating Frequency (MHz) DDR200 DDR266A DDR333 -8 -7 -6 100 133 133 125 143 166 • Double data rate architecture: two data transfers

P-TSOPII-54

Abstract: PC133 registered reference design
Contextual Info: HYB39S512400/800/160AT L 512MBit Synchronous DRAM 512 MBit Synchronous DRAM Preliminary Datasheet April ’01 • High Performance: -6 -7 -7.5 -8 Units fCK 166 143 133 125 MHz tCK3 6 7 7.5 8 ns tAC3 5 5.4 5.4 6 ns tCK2 7.5 7.5 10 10 ns tAC2 5.4 5.4 6 6 ns

P-TSOPII-54

Abstract: 39s64160at-8
Contextual Info: HYB39S64400/800/160AT L 64MBit Synchronous DRAM 64 MBit Synchronous DRAM • High Performance: -8 -8B -10 Units fCKmax. 125 100 100 MHz tCK3 8 10 10 ns tAC3 6 6 7 ns tCK2 10 12 15 ns tAC2 6 7 8 ns • Fully Synchronous to Positive Clock Edge • 0 to 70 °C operating temperature

BA0A11

Contextual Info: SIEMENS HYB39S64400/800/160AT L 64MBit Synchronous DRAM 64 MBit Synchronous DRAM • High Performance: Multiple Burst Operation -8 -10 Units fCKmax. 125 100 MHz tCK3 8 10 ns tAC3 6 7 ns tCK2 10 15 ns tAC2 6 8 ns Automatic Command and Read with Single Write

PC100-222-620

Abstract: PC133-333-520 P-TSOPII-54 pc100-322-620 SMD MARKING CODE M3
Contextual Info: HYB 39S256400/800/160AT 256-MBit Synchronous DRAM 256-MBit Synchronous DRAM • Multiple Burst Read with Single Write Operation • High Performance: • Automatic and Controlled Precharge Command -7.5 -8 -8A -8B Units fCK 133 125 125 100 MHz tCK3 7.5 8 8

HYB25D512800AT

Abstract: TSOP-66
Contextual Info: HYB25D512400/800/160AT L 512-MBit Double Data Rata SDRAM Preliminary Datasheet V0.91, 2002-11-14 Features CAS Latency and Frequency CAS Latency 2 2.5 Maximum Operating Frequency (MHz) DDR200 DDR266A DDR333 -8 -7 -6 100 133 133 125 143 166 • Double data rate architecture: two data transfers

Contextual Info: SIEMENS HYB39S64400/800/160AT L 64MBit Synchronous DRAM 64 MBit Synchronous DRAM • High Performance: Multiple Burst Operation -8 -8B -10 Units fCKmax. 125 100 100 MHz tCK3 8 10 10 ns tAC3 6 6 7 ns tCK2 10 12 15 ns tAC2 6 7 8 ns Automatic Command and Read

Contextual Info: SIEM ENS 16 MBit Synchronous DRAM second generation HYB 39S16400/800/160AT-8/-10 Advanced Information • High Performance: CAS latency = 3 Multiple Burst Read with Single Write Operation -8 -10 Units 125 100 MHz Automatic and Controlled Precharge Command

Contextual Info: HYB25D128400/800/160AT L 128-Mbit Double Data Rate SDRAM Features CAS Latency and Frequency CAS Latency 2 2.5 Maximum Operating Frequency (MHz) DDR200 DDR266A DDR333 -8 -7 -6 100 133 133 125 143 166 • Double data rate architecture: two data transfers per clock cycle

Contextual Info: HYB 39S256400/800/160AT 256-MBit Synchronous DRAM 256-MBit Synchronous DRAM Preliminary Information • Multiple Burst Read with Single Write Operation • High Performance: • Automatic and Controlled Precharge Command -7.5 -8 -8A -8B Units fCK 133 125 125

TSOP66

Contextual Info: HYB25D512400/800/160AT L /AC(L) 512-MBit Double Data Rata SDRAM Preliminary Version 12/01 Features CAS Latency and Frequency CAS Latency 2 2.5 Maximum Operating Frequency (MHz) DDR200 DDR266A DDR333 -8 -7 -6 100 133 133 125 143 166 • Double data rate architecture: two data transfers

39S16800AT-8

Abstract: 39S16800AT-10
Contextual Info: SIEMENS 16 MBit Synchronous DRAM second generation HYB 39S16400/800/160AT-8/-10 Advanced Information High Performance: -8 -10 Units /CK 125 100 MHz Automatic and Controlled Precharge Command CO Multiple Burst Read with Single Write Operation o • 8 10 ns

39S16800AT-8

Abstract: smd marking m11 Q67100-Q1323 Q67100-Q1333 Q67100-Q1335 39S16800T 39S16800AT-10 smd marking code M11 smd code m6
Contextual Info: 16 MBit Synchronous DRAM second generation HYB 39S16400/800/160AT-8/-10 Advanced Information • High Performance: CAS latency = 3 • Multiple Burst Read with Single Write Operation -8 -10 Units fCK 125 100 MHz • Automatic and Controlled Precharge Command

Contextual Info: 4M x 16-Bit Dynamic RAM 8k, 4k & 2k Refresh HYB 160AT(L) -40/-50/-60 HYB 160AT(L) -40/-50/-60 HYB 160AT(L) -40/-50/-60 Advanced Information • 4 194 304 words by 16-bit organization • 0 to 70 °C operating temperature • Fast Page Mode operation

39S256160T

Abstract: PC100-333-620 IT191 s4 marking code siemens SMD MARKING CODE A12 smd marking KH P-TSOPII-54
Contextual Info: H Y B 39S 25 640 0/8 00/1 60 T 256M B it S ynch ro n o u s DRAM S IE M E N S 2 5 6 M B it S y n c h ro n o u s D R A M P re lim in a ry In fo rm a tio n • High Perform ance: Multiple Burst Operation -8 -8B -10 Units fC K 125 100 100 M Hz tC K 3 8 10 10 ns

39S256160T

Abstract: PC100-322-620 smd CAY PC100-322 P-TSOPII-54
Contextual Info: HYB39S256400/800/160T 256MBit Synchronous DRAM 256 MBit Synchronous DRAM Preliminary Information • High Performance: -8 -8A -8B Units fCK 125 125 100 MHz tCK3 8 8 10 ns tAC3 6 6 6 ns tCK2 10 12 15 ns tAC2 6 6 7 ns • Fully Synchronous to Positive Clock Edge

101ZZ

Abstract: m1s23 PDCR 900 TLCS-900 TMP94C241C TMP94C241CF M2S22 PDCR 940 MNS20 B5WR
Contextual Info: TOSHIBA TMP94C241C CMOS 32-bit Microcontroller TMP94C241CF 1. O u t lin e an d Device Characteristics TMP94C241C is high-speed advanced 32-bit micro-controller developed for controlling equipment which processes mass data. TMP94C241C is a micro-controller which has a high-performance CPU 900/H2 CPU and various

16-DRAM

Abstract: HYB3164160AT TSOP 50 Package
Contextual Info: 4M x 16-Bit Dynamic RAM 8k, 4k & 2k Refresh HYB 160AT(L) -40/-50/-60 HYB 160AT(L) -40/-50/-60 HYB 160AT(L) -40/-50/-60 Advanced Information • 4 194 304 words by 16-bit organization • 0 to 70 °C operating temperature • Fast Page Mode operation

Contextual Info: # H YB39S256400/800/160T 256MBit Synchronous DRAM In fin eon 256 MBit Synchronous DRAM Preliminary Information • High Performance: Multiple Burst Operation -8 -8A -8B Units fC K 125 125 100 M Hz tC K 3 8 8 10 ns tA C 3 6 6 6 ns tC K 2 10 12 15 ns tA C 2

Contextual Info: SIEMENS 256 MBit Synchronous DRAM HYB 39S256400/800/160T Preliminary Information • High Performance: Multiple Burst Read with Single W rite Operation -8 -8B -10 Units 125 100 100 MHz fCK3 8 10 10 ns Data M ask for Read/W rite control fAC3 6 6 7 ns Data M ask for byte control