Please enter a valid full or partial manufacturer part number with a minimum of 3 letters or numbers

    144PIN ASIC Search Results

    144PIN ASIC Result Highlights (2)

    Part ECAD Model Manufacturer Description Download Buy
    ADUCM356BCCZ Analog Devices Smart Sensor ASSP/ASIC with 25 Visit Analog Devices Buy
    ADL5591ACPZ-R7 Analog Devices EMOD GSM ASIC FOR ERICSSON 180 Visit Analog Devices Buy

    144PIN ASIC Datasheets Context Search

    Catalog Datasheet MFG & Type PDF Document Tags

    16X24B

    Abstract: CF160 PF100 PF144 PL84 CPGA Package Diagram
    Text: QL16x24B pASIC 1 Family Very-High-Speed CMOS FPGA Rev C pASIC HIGHLIGHTS …4,000 usable ASIC gates, 122 I/O pins Very High Speed – ViaLink metal-to-metal programmable–via antifuse technology, allows counter speeds over 150 MHz and logic cell delays of under 2 ns.


    Original     		PDF QL16x24B 16-by-24 84-pin 100-pin 144-pin 160-pin 16-bit 16x24B CF160 PF100 PF144 PL84 CPGA Package Diagram

    QL4090

    Abstract: pASIC 1 Family 160CQFP 208-CQFP
    Text: QL16x24B pASIC 1 Family Very-High-Speed CMOS FPGA Rev C pASIC HIGHLIGHTS …4,000 usable ASIC gates, 122 I/O pins Very High Speed – ViaLink metal-to-metal programmable–via antifuse technology, allows counter speeds over 150 MHz and logic cell delays of under 2 ns.


    Original     		PDF QL16x24B 16-by-24 84-pin 100-pin 144-pin 160-pin 16-bit V144-TQFP QL24x32B QL4090 pASIC 1 Family 160CQFP 208-CQFP

    144pin asic

    Abstract: Photo resistor datasheet
    Text: SYSTEM ASIC Design Solution SYSTEM ASIC Design Solution Advanced Wafer Process High Quality Design User Friendly EDA Ultra Small Package Compatible with multi-purpose user-friendly EDA tools ROHM ASIC 's and EDA tools Cell Based IC Tool Entry Entry/simulator


    Original     		PDF BU35Sfamily BU25Sfamily BU16Sfamily 144pin) 144pin asic Photo resistor datasheet

    d65641gd

    Abstract: D65656 D65801GD D65806 D65808 D65640GC nec 44-pin LQFP d65611gb D65625GC d65626gf D65672GL
    Text: NEC ELECTRONICS INC. October 1999 TRQ-99-10-335 QUARTERLY ASIC RELIABILITY REPORT This report contains reliability data on the following application-specific integrated circuit families fabricated and assembled by NEC Japan BiCMOS-4/4A BiCMOS-5 ECL-2 ECL-3/3A/3B


    Original     		PDF TRQ-99-10-335 304-pin d65641gd D65656 D65801GD D65806 D65808 D65640GC nec 44-pin LQFP d65611gb D65625GC d65626gf D65672GL

    antifuse programming technology

    Abstract: ql24x32b PF144 PQ208 QL24X32B-1PQ208C
    Text: QL24x32B pASIC 1 Family Very-High-Speed CMOS FPGA pASIC HIGHLIGHTS …8,000 usable ASIC gates, 180 I/O pins Very High Speed – ViaLink metal-to-metal programmable–via antifuse technology, allows counter speeds over 150 MHz and logic cell delays of under 2 ns.


    Original     		PDF QL24x32B 24-by-32 144-pin 208-pin 24x32B PQ208 M/883C PF144 antifuse programming technology ql24x32b PF144 QL24X32B-1PQ208C

    PF144

    Abstract: PQ208 QL24X32B-1PQ208C
    Text: QL24x32B pASIC 1 Family Very-High-Speed CMOS FPGA pASIC HIGHLIGHTS …8,000 usable ASIC gates, 180 I/O pins Very High Speed – ViaLink metal-to-metal programmable–via antifuse technology, allows counter speeds over 150 MHz and logic cell delays of under 2 ns.


    Original     		PDF QL24x32B 24-by-32 144-pin 208-pin 24x32B PQ208 M/883C PF144 PF144 QL24X32B-1PQ208C

    PF144

    Abstract: PQ208 QL24X32B-1PQ208C 208-Pin CQFP
    Text: QL24x32B 5.0V pASIC 1 Family Very-High-Speed CMOS FPGA pASIC HIGHLIGHTS …8,000 usable ASIC gates, 180 I/O pins Very High Speed – ViaLink metal-to-metal programmable–via antifuse technology, allows counter speeds over 150 MHz and logic cell delays of under 2 ns at 5V, and over 80 MHz at 3.3V operation.


    Original     		PDF QL24x32B 24-by-32 144-pin 208-pin 24x32B PQ208 M/883C PF144 PF144 QL24X32B-1PQ208C 208-Pin CQFP

    FPGA 144 CPGA 172 PLCC ASIC

    Abstract: pASIC 1 Family 883-MIL
    Text: QL24x32B pASIC 1 Family Very-High-Speed CMOS FPGA pASIC HIGHLIGHTS …8,000 usable ASIC gates, 180 I/O pins Very High Speed – ViaLink metal-to-metal programmable–via antifuse technology, allows counter speeds over 150 MHz and logic cell delays of under 2 ns.


    Original     		PDF QL24x32B 24-by-32 144-pin 208-pin w144-TQFP 208-PQFP 208-CQFP 125oC FPGA 144 CPGA 172 PLCC ASIC pASIC 1 Family 883-MIL

    EPF10K30EQC208-1

    Abstract: TMS3450 EPF10K30EQC208-3
    Text: LIBERATOR CL10K30E Key Features u Fully Compatible to the Altera FLEX® 10KE Family u Prototype Your System With Altera FPGAs Y R A u Seamlessly Migrate Production To Clear Logic u No ASIC Engineering, No NRE, And No Test Vector Development N I M u Very Fast, Dense Signal Routing Using Vertical Link


    Original     		PDF CL10K30E CL10KE CL10K50E CL10K50S CL10K100E CL10K200E CL10K200S 84-1X* EPF10K30EFC484-1X EPF10K30EQC208-1 TMS3450 EPF10K30EQC208-3

    Untitled

    Abstract: No abstract text available
    Text: LIBERATOR CL10K30E Key Features u Fully Compatible to the Altera FLEX® 10KE Family u Prototype Your System With Altera FPGAs Y R A u Seamlessly Migrate Production To Clear Logic u No ASIC Engineering, No NRE, And No Test Vector Development N I M u Very Fast, Dense Signal Routing Using Vertical Link


    Original     		PDF CL10K30E CL10KE CL10K50E CL10K50S CL10K100E CL10K200E CL10K200S 84-1X* EPF10K30EFC484-1X

    TMS3450

    Abstract: EPF1K30TC144 CL10K-based 1K30 EPF1K30TC144-3 EPF1K30TC144-2 EPF1K EPF1K30FC256-1 CL1K EPF1K30FC256-3
    Text: LIBERATOR Key Features CL1K30 u Fully Compatible to the Altera ACEX® 1K Family u Prototype Your System With Altera FPGAs Y R A u Seamlessly Migrate Production To Clear Logic u No ASIC Engineering, No NRE, And No Test Vector Development N I M u Very Fast, Dense Signal Routing Using Vertical Link


    Original     		PDF CL1K30 CL1K50 CL1K100 CL1K30TC144-3 EPF1K30TC144-3 CL1K30TC144-2 EPF1K30TC144-2 CL1K30TC144-1 TMS3450 EPF1K30TC144 CL10K-based 1K30 EPF1K30TC144-3 EPF1K30TC144-2 EPF1K EPF1K30FC256-1 CL1K EPF1K30FC256-3

    EP1K50TC144-3

    Abstract: EP1K50QC208-3 TMS3450 ep1k50tc144 EP1K50 EP1K50FC256-1 EP1K50FC484-3 ep1K50QC208-3 Datasheet EP1K50TC144-1 EP1K50TC144-2
    Text: LIBERATOR Key Features CL1K50 u Fully Compatible to the Altera ACEX® 1K Family u Prototype Your System With Altera FPGAs Y R A u Seamlessly Migrate Production To Clear Logic u No ASIC Engineering, No NRE, And No Test Vector Development N I M u Very Fast, Dense Signal Routing Using Vertical Link


    Original     		PDF CL1K50 CL1K30 CL1K100 CL1K50TC144-3 EP1K50TC144-3 CL1K50TC144-2 EP1K50TC144-2 CL1K50TC144-1 EP1K50TC144-1 EP1K50TC144-3 EP1K50QC208-3 TMS3450 ep1k50tc144 EP1K50 EP1K50FC256-1 EP1K50FC484-3 ep1K50QC208-3 Datasheet EP1K50TC144-1 EP1K50TC144-2

    TMS3450

    Abstract: CL10K200E
    Text: LIBERATOR Key Features CL10K50E u Fully Compatible To The Altera FLEX® 10KE Family u Prototype Your System With Altera FPGAs Y R A u Seamlessly Migrate Production To Clear Logic u No ASIC Engineering, No NRE, And No Test Vector Development N I M u Very Fast, Dense Signal Routing Using Vertical Link


    Original     		PDF CL10K50E CL10KE CL10K30E CL10K50S CL10K100E CL10K200E CL10K200S 84-1X* EPF10K30EFC484-1X TMS3450 CL10K200E

    9560a

    Abstract: epm tqfp-144 484 pin BGA diagram 144-Pin PLCC/TQFP Package Pin-Out Diagram EPM3128A 256 pin diagram 10k50 Power PQFP 64 Altera 7032 FLEX 6000 144-Pin PLCC/TQFP Package Pin-Out D
    Text: ¨ Component Selector Guide June 1999 S System-on-a-ProgrammableChip Solutions In today’s changing marketplace, time-to-market is the key to success. Altera’s product offerings help companies get to market first by addressing a wide range of needs from simple glue logic requirements to the challenges


    Original     		PDF 7000E, 7000S, M-SG-COMP-06 9560a epm tqfp-144 484 pin BGA diagram 144-Pin PLCC/TQFP Package Pin-Out Diagram EPM3128A 256 pin diagram 10k50 Power PQFP 64 Altera 7032 FLEX 6000 144-Pin PLCC/TQFP Package Pin-Out D

    C5410

    Abstract: TMS320VC5410 TMS320VC5410PGE100 "california devices" hcs
    Text: DSP HeLP-Stack DPHD15410SM16Q-10 DESCRIPTION: HeLP-Stack™ is a family of products that stack DSPs digital signal processors , ASICs (application specific integrated circuits), PLDs (programmable logic devices), memory and other logic components. This allows system designers to


    Original     		PDF DPHD15410SM16Q-10 DPHD15410SM16Q-10 TMS320VC5410 C5410) 10MHz TMS320VCQUAD 30A247-00 C5410 TMS320VC5410 TMS320VC5410PGE100 "california devices" hcs

    TMS3450

    Abstract: epf10k30etc144-3
    Text: LIBERATOR Key Features CL10K50E u Fully Compatible To The Altera FLEX® 10KE Family u Prototype Your System With Altera FPGAs Y R A u Seamlessly Migrate Production To Clear Logic u No ASIC Engineering, No NRE, And No Test Vector Development N I M u Very Fast, Dense Signal Routing Using Vertical Link


    Original     		PDF CL10K50E CL10KE CL10K30E CL10K50S CL10K100E CL10K200E CL10K200S 84-1X* EPF10K30EFC484-1X TMS3450 epf10k30etc144-3

    EPF10K50SFC484-2X

    Abstract: TMS3450 EPF10K50sqc208-2 EPF10K50SQI208-2
    Text: LIBERATOR Key Features CL10K50S u Fully Compatible to the Altera FLEX® 10KS Family u Prototype Your System With Altera FPGAs Y R A u Seamlessly Migrate Production To Clear Logic u No ASIC Engineering, No NRE, And No Test Vector Development N I M u Very Fast, Dense Signal Routing Using Vertical Link


    Original     		PDF CL10K50S CL10KE CL10K30E CL10K50E CL10K100E CL10K200E CL10K200S CL10K50SBC356-3 EPF10K50SBC356-3 EPF10K50SFC484-2X TMS3450 EPF10K50sqc208-2 EPF10K50SQI208-2

    EPF10K50SFC484-3

    Abstract: diode t25 4 L9 EPF10K50SQC208-2X TMS3450 EPF10K50SQC240 EPF10K50SQC240-1 EPF10K50SQC240-2X
    Text: LIBERATOR Key Features CL10K50S u Fully Compatible to the Altera FLEX® 10KS Family u Prototype Your System With Altera FPGAs Y R A u Seamlessly Migrate Production To Clear Logic u No ASIC Engineering, No NRE, And No Test Vector Development N I M u Very Fast, Dense Signal Routing Using Vertical Link


    Original     		PDF CL10K50S CL10KE CL10K30E CL10K50E CL10K100E CL10K200E CL10K200S CL10K50SBC356-3 EPF10K50SBC356-3 EPF10K50SFC484-3 diode t25 4 L9 EPF10K50SQC208-2X TMS3450 EPF10K50SQC240 EPF10K50SQC240-1 EPF10K50SQC240-2X

    CF160

    Abstract: PF100 PF144 PL84
    Text: QL16x24B 5.0V pASIC 1 Family Very-High-Speed CMOS FPGA Rev C pASIC HIGHLIGHTS Very High Speed – ViaLink metal-to-metal programmable–via antifuse technology, allows counter speeds over 150 MHz and logic cell delays of under 2 ns at 5V, and over 80 MHz at 3.3V operation.


    Original     		PDF QL16x24B 16-by-24 84-pin 100-pin 144-pin 160-pin 16-bit 16x24B PF144 CF160 PF100 PL84

    PL84C

    Abstract: CPGA Package Diagram TQFP 10 10
    Text: QL16x24B pASIC 1 Family Very-High-Speed CMOS FPGA Rev C pASIC HIGHLIGHTS .4,000 usable ASIC gates, 122 I/O pins Very High Speed - ViaLink" metal-to-metal programmable-via antifuse technology, allows counter speeds over 150 MHz and logic cell delays of under 2 ns.


    OCR Scan     		PDF QL16x24B 16-by-24 84-pin 100-pin 144-pin 160-pin 16-bit 16x24B PF144C PL84C CPGA Package Diagram TQFP 10 10

    Untitled

    Abstract: No abstract text available
    Text: Q L16X24B pASIC 1 Family Very-High-Speed CMOS FPGA Rev C pASIC HIGHLIGHTS .4,000 usable ASIC gates, 122 I/O pins Very High Speed - ViaLink metal-to-metal program m able-via antifuse technology, allows counter speeds over 150 MHz and logic cell delays of under 2 ns.


    OCR Scan     		PDF L16X24B 16-by-24 84-pin 100-pin 144-pin 160-pin 16-bit 16x24B PF144C

    Untitled

    Abstract: No abstract text available
    Text: QL16X24BL pASIC 1 Family Low Power 3.3 Volt Operation FPGA pASIC HIGHLIGHTS .4,000 usable ASIC gates, 122 I/O pins S 5V Tolerant I/Os - Support interface to 5 Volt CMOS, NMOS and bipolar devices by sinking up to 12 mA see IIH specification . S High Usable Density - A 16-by-24 array of 384 logic cells


    OCR Scan     		PDF QL16X24BL 16-by-24 84-pin 100-pin 144-pin QL16x24B 16X24BL PF144 PF100

    ic 431

    Abstract: QBS3
    Text: Q L 24x32B pASIC 1 Family Very-High-Speed CMOS FPGA pASIC HIGHLIGHTS .8,000 usable ASIC gates, 180 I/O pins Very High Speed - ViaLink® metal-to-metal programmable-via antifuse technology, allows counter speeds over 150 MHz and logic cell delays of under 2 ns.


    OCR Scan     		PDF 24x32B 24-by-32 144-pin 208-pin 24x32B PQ208 M/883C PF144 ic 431 QBS3

    Untitled

    Abstract: No abstract text available
    Text: CY7C387A CY7C388A ¿r C Y P R E S S Very High Speed 8K 24K Gate CMOS FPGA Features — 16-bit counter operating at 100 MHz consumes 50 mA — Minimum Iql of 12 mA and Iqh of 8 mA • Very high speed — Loadable counter frequencies greater than 150 MHz — Chip-to-chip operating frequencies


    OCR Scan     		PDF CY7C387A CY7C388A 145-pin 144-pin 208-pin 160-pin 16-bit