140PS Search Results

hp310

Contextual Info: SN65LVDS16, SN65LVP16 SN65LVDS17, SN65LVP17 www.ti.com SLLS625B – SEPTEMBER 2004 – REVISED NOVEMBER 2005 2.5-V/3.3-V OSCILLATOR GAIN STAGE/BUFFERS • FEATURES • • • Low-Voltage PECL Input and Low-Voltage PECL or LVDS Outputs Clock Rates to 2 GHz

Contextual Info: DS90CR287,DS90CR288A DS90CR287/DS90CR288A +3.3V Rising Edge Data Strobe LVDS 28-Bit Channel Link-85 MHz Literature Number: SNLS056F DS90CR287/DS90CR288A +3.3V Rising Edge Data Strobe LVDS 28-Bit Channel Link-85 MHz General Description Features The DS90CR287 transmitter converts 28 bits of LVCMOS/

S1D15719

Abstract: S1D15722D01B S1D15719D22B S1D15714D01E s1d13517 S1D15722 Matrix CCD "line sensor" Epson epd driving S1D15712 S1D15721D01B
Contextual Info: CMOS LSIs Product Catalog 2009 SEIKO EPSON CORPORATION CMOS LSIs Contents Configuration of product number . 2 1 ASICs Application Specific IC 1-1 Gate Arrays . 4

32-PIN

Abstract: ICS85310AYI-01 ICS85310I-01 MC100LVEP111 MS-026
Contextual Info: Integrated Circuit Systems, Inc. ICS85310I-01 LOW SKEW, 1-TO-10 DIFFERENTIAL-TO-2.5V/3.3V ECL/LVPECL FANOUT BUFFER GENERAL DESCRIPTION FEATURES The ICS85310I-01 is a low skew, high performance 1-to-10 Differential-to-2.5V/3.3V ECL/ HiPerClockS LVPECL Fanout Buffer and a member of the

Contextual Info: DS90CR287/DS90CR288A +3.3V Rising Edge Data Strobe LVDS 28-Bit Channel Link-85 MHz General Description Features The DS90CR287 transmitter converts 28 bits of LVCMOS/ LVTTL data into four LVDS Low Voltage Differential Signaling data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fifth LVDS link.

Contextual Info: 2Gb: x8, x16 DDR3L-RS SDRAM Description 1.35V DDR3L-RS SDRAM MT41K256M8 – 32 Meg x 8 x 8 banks MT41K128M16 – 16 Meg x 16 x 8 banks Description Features DDR3L-RS SDRAM 1.35V is a low current self refresh version, via a TCSR feature, of the DDR3L SDRAM

MT41K512M8RH

Abstract: 901KB MT41K256M16 MT41K512M8RH-125 256M16 A2 SMD CODE MARKING MT41K512M8RH-125M DDR3L
Contextual Info: 4Gb: x4, x8, x16 DDR3L-RS SDRAM Description 1.35V DDR3L-RS SDRAM MT41K1G4 - 128 Meg x 4 x 8 banks MT41K512M8 – 64 Meg x 8 x 8 banks MT41K256M16 – 32 Meg x 16 x 8 banks Description Features • Self refresh temperature SRT • Automatic self refresh (ASR)

96-ball FBGA

Contextual Info: 2Gb: x8, x16 DDR3Lm SDRAM Description 1.35V DDR3Lm SDRAM MT41K256M8 – 32 Meg x 8 x 8 banks MT41K128M16 – 16 Meg x 16 x 8 banks Description Features • • • • • • Self refresh temperature SRT Automatic self refresh (ASR) Write leveling Multipurpose register

MT41K128M16

Abstract: MT41K128M1 TIS87 AC135 MT41K256 MT41K128M 140-RT-T MT41K
Contextual Info: 2Gb: x8, x16 DDR3Lm SDRAM Description 1.35V DDR3Lm SDRAM MT41K256M8 – 32 Meg x 8 x 8 banks MT41K128M16 – 16 Meg x 16 x 8 banks Description Features • TC of 0°C to +95°C – 64ms, 8192-cycle refresh at 0°C to +85°C – 32ms at +85°C to +95°C; See SRT

R1240

Abstract: PL138-28
Contextual Info: Preliminary PL138-28 2.5V-3.3V Low-Skew 1-2 Differential PECL Fanout Buffer FEATURES DESCRIPTION • Two differential 2.5V/3.3V LVPECL output pairs.  Output Frequency: ≤ 1 GHz.  Translates any standard single-ended or differential input format to LVPECL output. It can accept the

DS90CR287

Abstract: DS90CR287MTD DS90CR288A DS90CR288AMTD MTD56
Contextual Info: DS90CR287/DS90CR288A +3.3V Rising Edge Data Strobe LVDS 28-Bit Channel Link-85 MHZ General Description Features The DS90CR287 transmitter converts 28 bits of CMOS/TTL data into four LVDS Low Voltage Differential Signaling data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fifth LVDS link. Every cycle

Contextual Info: SN65LVDS16, SN65LVP16 SN65LVDS17, SN65LVP17 www.ti.com SLLS625B – SEPTEMBER 2004 – REVISED NOVEMBER 2005 2.5-V/3.3-V OSCILLATOR GAIN STAGE/BUFFERS • FEATURES • • • Low-Voltage PECL Input and Low-Voltage PECL or LVDS Outputs Clock Rates to 2 GHz

Contextual Info: 19-2130; Rev 2; 11/10 KIT ATION EVALU ABLE AVAIL 10-Bit Bus LVDS Deserializers The MAX9206/MAX9208 deserializers transform a highspeed serial bus low-voltage differential signaling BLVDS data stream into 10-bit-wide parallel LVCMOS/ LVTTL data and clock. The deserializers pair with serializers such as the MAX9205/MAX9207, which generate a serial BLVDS signal from 10-bit-wide parallel

JUX connector

Contextual Info: JUX CONNECTOR 0.6mm pitch/Board-to-board connectors • With guide system for mating • Outstanding click feeling when mating • Space saving • Vertical and horizontal mounting Specifications ––––––––––––––––––– • Current rating: 0.5A AC, DC

MT41K512M8RH-125

Abstract: 256M16
Contextual Info: 4Gb: x4, x8, x16 DDR3L SDRAM Description 1.35V DDR3L SDRAM MT41K1G4 – 128 Meg x 4 x 8 banks MT41K512M8 – 64 Meg x 8 x 8 banks MT41K256M16 – 32 Meg x 16 x 8 banks Description • TC of 0°C to +95°C – 64ms, 8192-cycle refresh at 0°C to +85°C – 32ms at +85°C to +95°C

0809g

Abstract: ICS9214
Contextual Info: ICS9214 Integrated Circuit Systems, Inc. Rambus TM TM XDR Clock Generator General Description Features The ICS9214 clock generator provides the necessary clock TM signals to support the Rambus XDR memory subsystem and Redwood logic interface. The clock source is a reference

sekisui 5760

Abstract: sis950 SiS chipset 486 SEAGATE st51080n Bt848KPF KSV884T4A1A-07 lad1 5vdc SiS chipset SiS301 kingmax usb flash drive
Contextual Info: SiS540 Super 7 2D/3D Ultra-AGPTM Single Chipset Content Figure .vi Table. vii

Contextual Info: PI3VDP411LSR Dual Mode DisplayPort to DVI/HDMI™ Electrical Bridge Level Shiter Features Description Î Converts low-swing AC coupled diferential input to Pericom Semiconductor’s PI3VDP411LSR provides the ability to use a Dual-mode DisplayPort™ transmitter in HDMI™ mode.

ta 933

Abstract: tr 337 WSON C101 SN65LVDS16 SN65LVDS17 SN65LVP16 SN65LVP17
Contextual Info: SN65LVDS16, SN65LVP16 SN65LVDS17, SN65LVP17 www.ti.com SLLS625B – SEPTEMBER 2004 – REVISED NOVEMBER 2005 2.5-V/3.3-V OSCILLATOR GAIN STAGE/BUFFERS • FEATURES • • • Low-Voltage PECL Input and Low-Voltage PECL or LVDS Outputs Clock Rates to 2 GHz

Contextual Info: Preliminary 2.5V-3.3V Low-Skew 1-2 Differential PECL Fanout Buffer FEATURES DESCRIPTION • Two differential 2.5V/3.3V LVPECL output pairs.  Output Frequency: ≤ 1 GHz.  Translates any standard single-ended or differential input format to LVPECL output. It can accept the

rambus xdr

Contextual Info: ICS9214 Integrated Circuit Systems, Inc. TM TM Rambus XDR Clock Generator General Description Features The ICS9214 clock generator provides the TMnecessary clock signals to support the Rambus XDR memory subsystem and Redwood logic interface. The clock source is a reference clock that may or may not be

85310AY-01

Abstract: ICS85310-01
Contextual Info: Integrated Circuit Systems, Inc. ICS85310-01 LOW SKEW, 1-TO-10 DIFFERENTIAL-TO-2.5V/3.3V ECL/LVPECL FANOUT BUFFER GENERAL DESCRIPTION FEATURES The ICS85310-01 is a low skew, high performance 1-to-10 Differential-to-2.5V/3.3V ECL/ HiPerClockS LVPECL Fanout Buffer and a member of the

hy5rs123235b

Abstract: HY5RS123235BFP HY5RS123235
Contextual Info: HY5RS123235BFP 512Mbit 16Mx32 GDDR3 SDRAM HY5RS123235BFP This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied.

Contextual Info: Integrated Circuit Systems, Inc. ICS85310I-11 LOW SKEW, 1-TO-10 DIFFERENTIAL-TO-2.5V/3.3V ECL/LVPECL FANOUT BUFFER GENERAL DESCRIPTION FEATURES The ICS85310I-11 is a low skew, high performance 1-to-10 Differential-to-2.5V/3.3V ECL/ HiPerClockS LVPECL Fanout Buffer and a member of the