1298H Search Results

Contextual Info: Features Datasheet RX64M Group Renesas MCUs R01DS0173EJ0100 Rev.1.00 Jul 31, 2014 120-MHz 32-bit RX MCU, on-chip FPU, 240 DMIPS, up to 4-MB flash memory, 512-KB SRAM, various communications interfaces including IEEE 1588-compliant Ethernet MAC, full-speed USB 2.0 with battery charging, SD host interface optional , quad SPI, and CAN, 12-bit A/D

1037h

Abstract: 1250H 1488h MX12 MX23 PM5365
Contextual Info: PM5365 TEMAP STANDARD PRODUCT DATASHEET PMC-1991148 ISSUE 3 HIGH DENSITY VT/TU MAPPER AND M13 MULTIPLEXER PM5365 TEMAP VT/TU MAPPER AND M13 MULTIPLEXER DATA SHEET PROPRIETARY AND CONFIDENTIAL RELEASED ISSUE 3: SEPTEMBER 2001 Proprietary and Confidential to PMC-Sierra, Inc. and for its Customers’ Internal Use

27291

Abstract: 80960RP MA11 272918 intel DOC
Contextual Info: 80960RP SPECIFICATION UPDATE Release Date: September, 1996 Order Number 272918-002 The 80960RP may contain design defects or errors known as errata. Characterized errata that may cause the 80960RP’s behavior to deviate from published specifications are documented in

Contextual Info: PM8315 TEMUX STANDARD PRODUCT DATASHEET ISSUE 7 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX :5 4: 01 AM PMC-1981125 co n Fr id ay ,2 TEMUX 9O ct ob er ,2 00 4 10 PM8315 DATASHEET PROPRIETARY AND CONFIDENTIAL ISSUE 7: MAY 2001 Do wn lo

HTR resistors

Abstract: 80960 80960SA reference i960 RP Processor 80960JF STT 433 1250H clock generator in dual core processor i960 Cx Instruction Set Quick Reference i960 Cx Processor Instruction Set Quick Reference
Contextual Info: i960 RP Microprocessor User’s Manual i960® RP Microprocessor User’s Manual February 1996 Order Number: 272736-001 Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for

80960

Abstract: BO 620 bbc timer stt 11 c17f i960 Cx Processor Instruction Set Quick Reference i960RP 80960JF 80960RD 80960RP MA11
Contextual Info: i960 Rx I/O Microprocessor Developer’s Manual Release Date: April, 1997 Order Number: 272736-002 The i960® Rx I/O Processor may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Such errata are

1587H

Contextual Info: PM8315 TEMUX PRELIMINARY DATASHEET PMC-981125 ISSUE 4 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MULTIPLEXER DATASHEET PROPRIETARY AND CONFIDENTIAL PRELIMINARY

0B-09

Abstract: bip 109
Contextual Info: PM5365 TEMAP PRELIMINARY DATASHEET PMC-991148 ISSUE 1 VT/TU MAPPER AND M13 MUX PM5365 TEMAP VT/TU MAPPER AND M13 MULTIPLEXER DATASHEET PROPRIETARY AND CONFIDENTIAL PRELIMINARY ISSUE 1: SEPTEMBER 1999 PMC-Sierra, Inc. 105 - 8555 Baxter Place Burnaby, BC Canada V5A 4V7 604 .415.6000

a8293

Abstract: A8294 A8264 PC 1498H 1250H a8296 BA RV cb rv 1050H REQ64
Contextual Info: Intel 80312 I/O Companion Chip Developer’s Manual December 2000 Order Number: 273410-002 Intel® 80312 I/O Companion Chip Information in this document is provided in connection with Intel® products. No license, express or implied, by estoppel or otherwise, to any intellectual

LB 124 d

Abstract: BH RV transistor i960 Cx Processor Instruction Set Quick Reference 80960JT 80960RM 80960RN REQ64 BIT3102 273160 80960
Contextual Info: i960 RM/RN I/O Processor Developer’s Manual July 1998 Order Number: 273158-001 Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability

GC80960RS100

Abstract: p16c182 P16C180V GC80960RN100 I960R 1250H capacitor 106c intel schematics 80960RM 80960RN
Contextual Info: Intel i960® RM/RN/RS I/O Processor Specification Update September 4, 2001 Notice: The 80960RM/RN/RS processor may contain design defects or errors known as errata. Characterized errata that may cause the product’s behavior to deviate from pubished specifications are documented in this specification update.

r602 transistor data

Abstract: transistor r601 U602 80960RM GC80960RN100 80960RN GC80960RM100 273164 PCI cyclone 3 schematics
Contextual Info: i960 RM/RN I/O Processor Specification Update March 1999 Notice: The 80960RM/RN may contain design defects or errors known as errata. Characterized errata that may cause 80960RM/RN’s behavior to deviate from pubished specifications are documented in this specification update.

diode K1V 452

Abstract: 09CCH 09E0H 09A1H 0943H 09C8 0951H 05C1H 1488h K1V 40 N
Contextual Info: SPECTRA-2488 Telecom Standard Product Data Sheet Released PM5315 SPECTRA-2488 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER FOR 2488 MBIT/S Data Sheet Proprietary and Confidential Released Issue 4: November, 2001 Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use

SI 1340H

Abstract: 1542H mx-126 1488h integrators si 1340h PSL 26 SA8 357 T1E1-7 DATA SHEET Equivalent MX12 MX23
Contextual Info: PM5365 TEMAP STANDARD PRODUCT REGISTER DESCRIPTION PMC-1990682 ISSUE 2 HIGH DENSITY VT/TU MAPPER AND M13 MULTIPLEXER PM5365 TEMAP HIGH DENSITY VT/TU MAPPER AND M13 MULTIPLEXER REGISTER DESCRIPTION Proprietary and Confidential ISSUE 2: JULY 2001 PMC-Sierra, Inc.

Contextual Info: PM8315 TEMUX PRELIMINARY DATASHEET PMC-1981125 ISSUE 5 HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MUX PM8315 TEMUX HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MULTIPLEXER DATASHEET PROPRIETARY AND CONFIDENTIAL PRELIMINARY

80960RM

Abstract: 80960RN GC80960RN100 U602 GC80960RM100 273164 PCI cyclone 3 schematics
Contextual Info: i960 RM/RN I/O Processor Specification Update January 1999 Notice: The 80960RM/RN may contain design defects or errors known as errata. Characterized errata that may cause 80960RM/RN’s behavior to deviate from pubished specifications are documented in this specification update.

1250H

Abstract: 1006H 100CH 100DH 1000H 103DH i960RP
Contextual Info: ACPI Implementation for the i960 RP/RD I/O Processor Application Note August 1999 Order Number: 273258-001 Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual

diode K1V 645

Abstract: 0923H 0A68H 1031f 09-D2 1182h 1488h ya11 PM5332-BI 1221H
Contextual Info: 28 AM SPECTRA 1x2488 ASSP Telecom Standard Product Data Sheet Released be r, 20 03 02 :5 7: PM5332 da y, 14 Oc to SPECTRA™ 1x2488 Data Sheet Released Issue No. 3: March 2003 lo ad ed by Am r Ma ns ou ro fS ilic on Ex pe rt Te cn ol og yI nc on Tu es SONET/SDH Payload Extractor/Aligner

1587H

Abstract: sdh demapper 1035H-1037H 1037h 1250H 1488h MX12 MX23 PM5365 9811J
Contextual Info: PM5365 TEMAP STANDARD PRODUCT DATASHEET ISSUE 3 HIGH DENSITY VT/TU MAPPER AND M13 MULTIPLEXER 11 :3 2: 49 PM PMC-1991148 ,1 1J an ua ry ,2 00 3 PM5365 to n Sa tu rd ay TEMAP DATA SHEET PROPRIETARY AND CONFIDENTIAL RELEASED ISSUE 3: SEPTEMBER 2001 Do wn lo

intel 8255

Abstract: 8255 intel microprocessor block diagram gigabyte MOTHERBOARD CIRCUIT diagram dac 8419 block diagram of intel 8255 chip GC80960RP3V33 gigabyte motherboard BUS BAR specification fast page mode dram controller microprocessor 8255 application
Contextual Info: i960 RP/RD I/O PROCESSOR SPECIFICATION UPDATE Release Date: March, 1999 Order Number: 272918-020 The i960® RP/RD I/O Processor may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are documented in this Specification Update.

8424h

Abstract: 1488h 1250H 103DH 1428H 1484H 1118H 8620H 1278H 8420H
Contextual Info: Memory-Mapped Registers C This chapter describes the memory-mapped registers for the integrated peripherals. C.1 Overview The Peripheral Memory-Mapped Register PMMR interface gives software the ability to read and modify internal control registers. Each register is accessed as a memory-mapped 32-bit register

Contextual Info: PM5365 TEMAP PRELIMINARY DATASHEET PMC-1991148 ISSUE 2 VT/TU MAPPER AND M13 MUX PM5365 TEMAP VT/TU MAPPER AND M13 MULTIPLEXER DATASHEET PROPRIETARY AND CONFIDENTIAL PRELIMINARY ISSUE 2: FEBRUARY 2000 PMC-Sierra, Inc. 105 - 8555 Baxter Place Burnaby, BC Canada V5A 4V7 604 .415.6000

1221h

Abstract: diode K1V 452 1488h AG18 1AB3 K1V 40 N PM5315 SPECTRA-2488 PMC 1601 001B PM5315
Contextual Info: PMC-Sierra, Inc. PRELIMINARY PM5315 SPECTRA-2488 DATASHEET PMC-1990821 ISSUE 3 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER FOR 2488 MBIT/S PM5315 SPECTRA-2488 SONET/SDH PAYLOAD EXTRACTOR/ALIGNER FOR 2488 MBIT/S DATASHEET PROPRIETARY AND CONFIDENTIAL PRELIMINARY ISSUE 2: FEBRUARY 2001

80960RM

Abstract: 80960RN GC80960RN100 GC80960RM100 273164 1298H 12c0h
Contextual Info: i960 RM/RN I/O Processor Specification Update October 1998 Notice: The 80960RM/RN may contain design defects or errors known as errata. Characterized errata that may cause 80960RM/RN’s behavior to deviate from pubished specifications are documented in this specification update.