120PL Search Results

tl741

Abstract: VEL-4P32-RH-TP sodium vapor lamp Magnetek ballast F32T8 transistor ballast 1000W VEL-3P32-RH-TP 13w cfl circuit D835 transistor PHILIPS T8 MAGNETIC BALLAST
Contextual Info: Manufacturers’ Cross Reference Guide These tables are intended only as guides and may represent another lamp/ballast company's most similar product rather than an identical match. Individual manufacturer's performance values should be consulted. For a complete cross reference guide please consult our electronic

XC-01

Abstract: D70236 smd 3F9 uPD72291 JUPD70236 interfacing of 8251 devices with 8085 high level language programming of 8085 microprocessor 8085 mnemonic opcode ls-112 TFK U 111 B
Contextual Info: NEC Electronics Inc. Description The V53 is a high-speed, high-integration 16-bit CM O S m icroprocessor with a CPU that is object and source code com patible with the V20 /V30®. Integrated on the same die is a 4-channel D M A controller, a DART, three

16S4P

Contextual Info: 7 8 THIS DRAWING IS UNPUBLISHED. C 6 5 4 3 2 RELEASED FOR PUBLICATION LOC 1 REVISIONS DIST ALL RIGHTS RESERVED. COPYRIGHT P LTR DESCRIPTION DATE DWN APVD DIM L REF D D DIM R DIM K DIM T TYP .930 .100 TYP C C Y .495 .278 2 PLC .574 .220 TAIL LENGTH TYP -A-

Contextual Info: Preliminary a Advanced Micro Devices Am79C864 Physical Layer Controller PLC DISTINCTIVE CHARACTERISTICS Implements FDDI PHY layer protocol for ISO standard (FDDI) 9314-1 • ■ Repeat Filter ■ Hardware Physical Connection Management (PCM) support ■

LPD-D

Abstract: sk2 354 SN74ABT3613 D1D1240
Contextual Info: SN74ABT3613 64 x 36 CLOCKED FIRST-IN, FIRST-OUT MEMORY WITH BUS MATCHING AND BYTE SWAPPING S C B 51 28 C - JULY 1992 - RE V IS E D M ARCH 1994 Free-Running CLKA and CLKB Can Be Asynchronous or Coincident 64 x 36 FIFO Buffering Data From Port A to Port B Mailbox Bypass Registers In Each

Contextual Info: FVeliminaiy n Advanced Micro Devices Am79C864 Physical Layer Controller PLC DISTINCTIVE CHARACTERISTICS Implements FDDI PHY layer protocol for ISO standard (FDDI) 9314-1 • Line state detection ■ ■ Hardware Physical Connection Management (PCM) support

NP920

Abstract: SUPERNET 2 Family pcms AM79C864A NP10 AMD Supernet am79864a AMD Supernet 2 NP5-12 NP1223
Contextual Info: PRELIMINARY Am79C864A Physical Layer Controller With Scrambler PLC-S Advanced Micro Devices DISTINCTIVE CHARACTERISTICS • Implements FDDI PHY layer protocol for ISO standard (FDDI) 9314-1 ■ Line state detection ■ Implements ANSI standard Stream Cipher

Contextual Info: SN74ACT7823 1024 X 36 CLOCKED FIRST-IN, FIRST-OUT MEMORY JUNE 1882 Member of the Texas Instruments Wldabus+ Family Free-Running CLKA and CLKB May Be Asynchronous or Coincident 1024 x 36 Clocked FIFO Buffering Data From Port A to Port B Retransmit Capability

nec v53 cpu

Abstract: 117 AJG cpu pc v53 PD70236 JUPD70236 nec upd70236 smd Code BKD interfacing of 8237 with 8085 6512a KRY 112 46
Contextual Info: SEC N E C ELECTRONICS INC 30E Q Description The V53m is a high-speed, high-integration 16-bit CMOS microprocessor with a CPU that is object and source code compatible with the V20 /V30®. Integrated on the same die is a 4-channel DMA controller, a UART, three

lem HA 10000

Abstract: Am79C864 NP10 1553S
Contextual Info: Preliminary Advanced Micro Devices Am79C864 Physical Layer Controller PLC DISTINCTIVE CHARACTERISTICS • ■ ■ ■ Implements FDDI PHY layer protocol for ISO standard (FDDI) 9314-1 Hardware Physical Connection Management (PCM) support Performs Physical Connection insertion and

EPM7160 Transition

Abstract: EPM7160-3 EPM7160 PLMJ7160-84 single one jk flipflop EPM7160-1 EPM7160-2 E7041 5628E
Contextual Info: EPM7160 EPLD AN b rs rA \ High-Performance 160-Macrocell Device Data Sheet September 1992, ver. 2 Features □ Preliminary Information □ □ □ □ □ □ □ □ □ □ High-density, erasable CMOS EPLD based on second-generation Multiple Array MatriX MAX architecture

25t65

Abstract: tl741 FBT Hr f8t5 bu 25200 F20T12 270033 TL835 F28T5 TL830
Contextual Info: Phillips Desc Philips Naed 36734-2 367342 375196 375196 37519-6 27556-0 27555-2 27558-6 209957 20995-7 38320-8 373902 373902 37390-2 246611 24661-1 299552 29955-2 299560 29956-0 347815 34781-5 348037 34803-7 37474-4 374769 37476-9 27086-8 239442 22300-8 370221

PJ 67 B6

Contextual Info: TEXAS INSTR ASIC/MEMORY b4E J> • flTbl725 DOAEbll TT4 ■ TII5 SN74ABT7817 64 X 36 CLOCKED FIRST-IN, FIRST-OUT MEMORY WITH BUS MATCHING AND BYTE SWAPPING SCBS128-JULY1992 Member of the Texas Instruments Wldebu8+ Family Free-Running CLKA and CLKB May Be

ceramic 1000p capacitors

Abstract: CA106 CN053 cn-033 4532 BD
Contextual Info: "fe T7 $ CERAMIC CAPACITORS nm E# Type Appearance Classification 1608 0603 □ M K 212 2125(0805) □ M K 316 3216(1206) □ M K 325 3225(1210) □ M K 432 4532(1812) □ M K 107 1608(0603) □ M K 212 2125(0805) □ M K 316 3216(1206) □ M K 325 3225(1210)

SN74ACT3631

Abstract: SN74ACT3641 SN74ACT3651 1A32J
Contextual Info: SN74ACT3651 2048 x 36 CLOCKED FIRST-IN, FIRST-OUT MEMORY SCAS439 - JUNE 1994 Output-Ready OR and Almost-Empty <AE) Flags Synchronized by CLKB Low-Power 0.8-Micron Advanced CMOS Technology Supports Clock Frequencies up to 67 MHz Fast Access Times of 11 ns

AM79C864

Abstract: ap1d
Contextual Info: ADV MI CR O TELEC OM MÖE D • 0257527 0D3GTM1, 5 ■ AMD3 Preliminary £1 Advanced Micro Devices Am79C864 Physical Layer Controller (PLC) DISTINCTIVE CHARACTERISTICS Implements FDDI PHY layer protocol for ISO standard (FDDI) 9314-1 M Line state detection

Contextual Info: 7 8 THIS DRAWING IS UNPUBLISHED. C COPYRIGHT 20 RELEASED FOR PUBLICATION 6 5 4 3 2 20 LOC BY - DIM L # .010 00 P LTR DESCRIPTION DATE DWN APVD M1 ADD NEW DASH NUMBER 7-0 08FEB2014 AL SZ M2 ADD NEW DASH NUMBER 21MAR2014 AL SZ 1 "AMP" PART NUMBER AND DATE CODE TO BE MARKED IN AREA SHOWN.

Contextual Info: Preliminary Advanced Micro Devices Am79C864 Physical Layer Controller PLC DISTINCTIVE CHARACTERISTICS • ■ ■ ■ Implements FDDI PHY layer protocol for ISO standard (FDDI) 9314-1 Hardware Physical Connection Management (PCM) support Performs Physical Connection insertion and

128pin

Abstract: IS81
Contextual Info: PACKAGE INFORMATION 933 I PACKAGE INFORMATION Unit: inch mm Plastic QFP6-fl0plr> 934 i PACKAGE INFORMATION Plastic QFPs Unit: inch (mm) Plastic QFP5-80pin-S2 Plastic QFP13-64pin Q.g13±QJW (23.21M ) 0.787*000« (20,0 ±o.i) 32 ir c T , If It §1 e s O“

BO-835

Abstract: l7 723 M/A nex es8 A17C IC51-1324-828 SN74ACT3631 SN74ACT3641 SN74ACT3651
Contextual Info: SN74ACT3631 512 x 36 CLOCKED FIRST-IN, FIRST-OUT MEMORY _ S C A S246B - A U G U S T 1993 - REVISED JUNE 1994 Free-Running CLKA and CLKB Can Be Asynchronous or Coincident Clocked FIFO Buffering Data From Port A to Port B Output-Ready OR and Almost-Empty (AE)

T7815

Abstract: F1F02
Contextual Info: SN74ABT7815 64 X 36 X 2 CLOCKED FIRST-IN, RRST-OUT MEMORY WITH BUS MATCHING AND BYTE SWAPPING S C B S 1 2 6 -JU N E 1992 Free-Running C L K A and CLKB May Be Asynchronous or Coincident EFK, FFA, AEA, and AFA Flags Synchronized by CLK A Two Independent 64 x 36 Clocked FIFOs

PMRL125W-BCG12H

Contextual Info: .230" PANEL MOUNT REFLECTOF [gIgJO ] T-1, Built-In Resistor, Water-Tight Options Data Display Products •Reflective Nickel-Plated Bod • Mounting Hardware Providec Maximum Panel Thickness .125" PMRL125); .070"(PMRL125, Water-Tight ■For Detailed LED Data, See Discrete Section, MODEL 12i

Contextual Info: 7 8 THIS DRAWING IS UNPUBLISHED. C COPYRIGHT 20 RELEASED FOR PUBLICATION BY - 6 5 4 3 2 20 LOC GP ALL RIGHTS RESERVED. DIM L # .010 D REVISIONS DIST 00 P 1 OPTIONAL CENTER MODULE, WITH 2 "AMP", PART NUMBER, AND DATE CODE TO BE MARKED IN AREA SHOWN. 3 4 2 1

ty 95 camping

Abstract: TPC1240
Contextual Info: TPC12 SERIES CMOS FIELD-PROGRAMMABLE GATE ARRAYS SRFS002C - D3963, DECEMBER 1991 - REVISED FEBRUARY 1993 Three Arrays With Increased Densities • Enhanced Architecture - Supports Single-Module Sequential Functions - Supports Wide-Input Combinatorial Functions