10ENT Search Results

Contextual Info: /T L in C A B TECHNOLOGY F€RTUR€S _ LTC1164-6 L o w P o w e r 8th O rd e r Pin S e le c t a b le E lliptic or Lin e a r P h a s e L o w p a ss Filter DCSCRIPTIOn • 8th Order Pin Selectable Elliptic or Bessel Filter in a The LTC1164-6 is a monolithic 8th order elliptic lowpass

ic la 1260

Contextual Info: Customer Information Shee □RAWING No.: Q0XXX-XX SHEET 2 OF 2 IF IN DOUBT - ASK NOT TO SCALE m ANGLE PROJECTION j ALL DIMENSIONS IN : ©©©©©©©! •12.95 - S T Y L E 'i' Ì L b fiO O O e O O ! i©"00©©©©0©i S T Y LE '2' i CL¿ I© ©©©©©©© ©i

Contextual Info: MN ETC-8 EmbeddedTestController The Micro Networks ETC-8 is an Embed­ Features: ded Test Controller designed for applica­ • Environmentally Rugged tion in diverse electronic and electrome­ chanical systems. The device and its real­ 9 TimeTag and Datalog

manual PACE PSR 800 Plus

Abstract: manual PACE PSR 900 manual PACE PSR 900 Plus 970fx PowerPC 970FX 970FX 1.41 a2b 340 manual PACE PSR 800 Developing Embedded Software For The IBM PowerPC 970FX Processor X0410
Contextual Info: Title Page IBM PowerPC 970FX RISC Microprocessor User’s Manual Version 1.7 March 14, 2008 Copyright and Disclaimer Copyright International Business Machines Corporation 2003, 2008 All Rights Reserved Printed in the United States of America March 2008

Contextual Info: N a tio n a l March 1996 Sem iconductor DM74ALS574A Octal D-Type Edge-Triggered Flip-Flop with TRI-STATE Outputs General Description These 8-bit registers feature totem-pole TRI-STATE outputs designed specifically for driving highiy-capacitive or relative­

Contextual Info: N _ , S e m i c o n d u c t o r a t i o n a l January 1992 MM54HC74A/MM74HC74A Dual D Flip-Flop with Preset and Clear General Description The 54HC/74HC logic family is functionally and pinout com­ patible with the standard 54LS/74LS logic family. All inputs

3 bit ripple counter

Abstract: 7493 counter chip ar 0330
Contextual Info: MM58167B EHNational mm S em iconductor MM58167B Microprocessor Real Time Clock General Description The MM58167B is a low threshold metal gate CMOS circuit that functions as a real time clock in bus oriented microproc­ essor systems. The device includes an addressable real

Contextual Info: Philips Semiconductors Preliminary specification 16-bit buffer/line driver; 3-State 74LVCH16541A FEATURES PIN CONFIGURATION • 5 volt tolerant inputs/outputs for interfacing with 5V togic • Wide supply voltage range of 1.2 V to 3.6 V • Complies with JEDEC standard no. 8-1A

SPARC64

Abstract: 180NM 400M GS21 sparc64 gp
Contextual Info: SPARC64 VII Fujitsu’s Next Generation Quad-Core Processor August 26, 2008 Takumi Maruyama LSI Development Division Next Generation Technical Computing Unit Fujitsu Limited All Rights Reserved,Copyright FUJITSU LIMITED 2008 Fujitsu Processor Development

MC88100

Abstract: M88000 MC88200 DA31-DA2 RISC semaphore 754for
Contextual Info: SEP 0 3 MOTOROLA O rder th is d o cu m e n t b y MC88100/D SEMICONDUCTOR TECHNICAL DATA M C 8 8 100 Technical Summary 32-Bit RISC Microprocessor The MC88100 is the first processor in the M88000 Family of reduced instruction set computer RISC microprocessors. Implemented with Motorola's HCMOS technology, the MC88100 incorporates 32-bit

E52283

Contextual Info: REV DATE DESCRIPTION SCO 100 112/93112741 RELEASED ! gr I CK m . •3/8 STUD K J e u J K K J L O ^ ^ *ir 0 Ì.Q&f P/N CONN TYPE 64011 64011R STUD 3. MATERIALS; BASE- PHENOLIC HARDWARE­ TIN PLATED COPPER ALLOY 2. REJECTION NOT SHOWN. 1. ADD R FOR REJECTION.

MC88200

Abstract: MC88100
Contextual Info: MOTOROLA Order this document by MC88200/D SEMICONDUCTOR TECHNICAL DATA MC88200 Technical Summary 16-Kbyte Cache/Memory Management Unit CM M U The MC88200 CMMU is a high-performance, HCMOS VLSI device providing zero-wait-state memory management and data caching. The memory management unit (MMU) efficiently supports a demand-paged

CORE i3 ARCHITECTURE

Abstract: CORE i3 instruction set SPARC64 core i7 registers SPARC64TM 220nm Fujitsu SparC64 instruction set sparc64viiifx core i7 alu fujitsu GS21
Contextual Info: SPARC64 VIIIfx: Fujitsu’s New Generation Octo Core Processor for PETA Scale computing August 25, 2009 Takumi Maruyama LSI Development Division Next Generation Technical Computing Unit Fujitsu Limited All Rights Reserved,Copyright FUJITSU LIMITED 2009

GI 312 diode

Abstract: mm-100-xx mm-100-xxx BTS 308 8x 8 led dot matrix amd 15h power AMD 754 AMD xp datasheet AMD64 Architecture Programmer Athlon 64
Contextual Info: Software Optimization Guide for AMD Athlon 64 and AMD Opteron™ Processors Publication # 25112 Revision: 3.03 Issue Date: September 2003 2001 – 2003 Advanced Micro Devices, Inc. All rights reserved. The contents of this document are provided in connection with Advanced Micro Devices,

Gigabyte 848p

Abstract: 82848P SRT 30130 848P 253575 MOTHERBOARD msi CIRCUIT diagram PC MOTHERBOARD CIRCUIT diagram gigabyte intel schematics
Contextual Info: Intel 848P Chipset Datasheet Intel® 82848P Memory Controller Hub MCH August 2003 Document Number: 253575-001 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN

deltabond 152

Abstract: deltabond
Contextual Info: REUc, vED M Ar 3 1995 DOnJMc NOTES: 1. DISSIPATION FACTOR: .0 0 5 MAX @ 25* C, 1 kHZ. 2 . CAPACITANCE: 45 n F - 5 5 nF. 3. DIELECTRIC WITHSTANDING VOLTAGE: 1.5 kV RATED, 2 .2 5 kV PROCESS FOR 2 HOURS @ 100* C AND 3 kV PROOF FOR 5 SECS. 4. GRIT BLAST FINISH, NO TAPE OVERWRAP.

96LS488

Abstract: CYB-002
Contextual Info: INTELLIGENT POSITIONING STEPPER MOTOR CONTROLLER 3F:CY512MAN.008 1 JUNE 83 ktm PRINTED IN U.S.A Cybernetic Micro Systems software products are copyrighted by and shall remain the property of Cybernetic Micro Systems, Inc. Duplication is subject to a license from Cybernetics. Cybernetic

tag l2

Abstract: PC2100 PC2700 X86-64 Northbridge L2 ecc x86 processor architecture Ht cpu support
Contextual Info: AMD’s Next Generation Microprocessor Architecture Fred Weber October 2001 "Hammer" Goals • Build a next-generation system architecture which serves as the foundation for future processor platforms • Enable a full line of server and workstation products

microprocessor 8212

Abstract: 970MP PowerPC 970MP kj 8445 TAG 8446 manual PACE PSR 800 Plus PowerPC Microprocessor Family Programming manual PACE PSR 900 x0227 manual PACE PSR 900 Plus
Contextual Info: Title Page IBM PowerPC 970MP RISC Microprocessor User’s Manual Version 2.3 March 7, 2008 Copyright and Disclaimer Copyright International Business Machines Corporation 2005, 2008 All Rights Reserved Printed in the United States of America March 2008

MC88100

Abstract: MC88200 ctp21 CTP01 MC88204
Contextual Info: 4. 1 U * ÌÌ MOTOROLA Order this document by MC88204/D • SEMICONDUCTOR TECHNICAL DATA Technical Sum m ary 64K-Byte Cache/Memory Management Unit CMMU The MC88204 CMMU is a high-performance, HCMOS VLSI device providing zero-wait-state memory management and data caching. The m emory management unit (MMU) efficiently

RM73B2B

Abstract: eta trw bead murata RM73B2BT102J VJ21 HLMP3301-010 HLMP3502 RM73B3A qi 20pin HFBR-5205
Contextual Info: I TEXAS INSTRUMENTS Semiconductor Group TNETA1561/TNETA1500 PCI Reference Schematic Notebook Physical Interface SONET 155-Mbit/s, Multimode Fiber Connector SD N V007 July 12,1995 Questions should be directed to: TNETA TECHNICAL SUPPORT LINE *4atm@.ti.com

LM709

Abstract: LM703 ML1015 LM709H ML-1015
Contextual Info: February 1995 Semicondu d o r LM709 Operational Amplifier General Description The LM709 series is a monolithic operational amplifier in­ tended for general-purpose applications. Operation is com­ pletely specified over the range of voltages commonly used

xc88200

Abstract: SADFL MC88200 TS832
Contextual Info: O THOMSON COMPOSANTS MILITAIRES ET SPATIAUX TS88200 16-KILOBYTE CACHE/MEMORY MANAGEMENT UNIT CMMU DESCR IPTIO N The TS88200 CMMU is a high-performance, HCMOS VLSI device providing zero-wait-state memory ma­ nagem ent and data caching. The MMU (memory management unit) e ffic ie n tly supports a demandpaged virtual memory environment with two logical

Contextual Info: in te i, 82078 64 PIN CHMOS SINGLE-CHIP FLOPPY DISK CONTROLLER • Small Footprint and Low Height Packages — Selectable Boot Drive — Standard IBM and ISO Format Features — Format with Write Command for High Performance in Mass Floppy Duplication ■ Supports Standard 5.0V as well as Low