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Contextual Info: Altera Software Installation and Licensing Subscribe Send Feedback MNL-1065 2013.11.04 101 Innovation Drive San Jose, CA 95134 www.altera.com TOC-2 Altera Software Installation and Licensing Contents Altera Software Installation and

Contextual Info: CXB1119Q SONY. Programmable Delay Line/Duty Cycle Controller Description Pin Assignment The C X B 1 11 9 Q is an ultra high speed monolithic ECL Delay Line/Duty Cycle Controller IC. Four binary inputs, So to S 3, program the delay time from input D in to output Qd in 16 steps.

d312

Abstract: 14.400mhz
Contextual Info: SMD Type VC- TCXO Module %4"."

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Contextual Info: SONY CORP/COMPONENT PRODS 50E D fl3û23fl3 0D03fl7b 3 «SO N Y CXB1119Q/Q-Y SO N Y. Programmable Delay Line/Duty Cycle Controller / 'V T ’- / 7 Description Pin Assignment The CXB1119Q is an ultra high speed monolithic ECL Delay Line/Duty Cycle Controller IC.

Contextual Info: 42E D 7^2=5237 0 0 3 b 2 0 4 S G S -T H O M S O N S ISGTH S G S-THOHSON TDA2320A • y -7 ¿ / - 0 5 - 0 I MINIDIP STEREO PREAMPLIFIER • WIDE SUPPLY VOLTAGE RANGE 3 TO 36V • SINGLE OR SPLIT SUPPLY OPERATION • VERY LOW (0.8mA) • VERY LOW DISTORTION

7WE37

Abstract: L0250 STP40N06 STP40N06FI V1068
Contextual Info: 7TETE37 QQ4hM7b Q7*\ » S f i T H STP40N06 STP40N06FI ¡ ñ l SGS-THOMSON ilLiOT «! N - CHANNEL ENHANCEMENT MODE POWER MOS TRANSISTOR TYPE V STP40N06 STP40N 06FI R oS o n Id < 0.035 n < 0.035 n 40 A 23 A dss 60 V 60 V . Q . TYPICAL RDS(on) = 0.03 AVALANCHE RUGGED TECHNOLOGY

apt10025

Contextual Info: • R r M ADVANCED A P T 10 0 2 5 JV R po w er Te c h n o l o g y 1000v 34a 0.250Q POWER MOS V Pow er M OS V is a new generation of high voltage N -C hannel enhancem ent m ode pow er M O SFE Ts. This new tech no lo gy m inim izes the JFE T effect, increases packing density and reduces the on-resistance. Pow er M OS V®

UAA2072M

Abstract: UMA1017M
Contextual Info: NAPC/PHILIPS SEMICOND b?E D • bbS3ci24 □ □a'JSBM 54T « S I C H Philip« Semiconductors RF Communication« Product« Objective specification Low-voltage frequency synthesizer for radiotelephones GENERAL DESCRIPTION FEATURES The BiCMOS device integrates prescaler,

2SC1594

Abstract: NE77320 33B5 NE77300 NE77310 NE77320T S21E S22E J25-26 1400 88 pm
Contextual Info: N E C / CALIFORNIA b42741M 1SE D 0 0 0 1 3 LjE 3 NE77300 NE77310 NE77320 NPN MEDIUM POWER MICROWAVE TRANSISTOR FEATURES DESCRIPTION AND APPLICATIONS • 2 WATTS POWER OUTPUT CLASS C AT 2 GHz The NE773 series of NPN medium power silicon transistors Is especially designed for broadband VHF and UHF amplifiers

CY7C1412BV18-200BZI

Abstract: CY7C1412BV18-167BZI CY7C1410BV18 CY7C1412BV18 CY7C1414BV18 CY7C1425BV18
Contextual Info: CY7C1410BV18 CY7C1425BV18 CY7C1412BV18 CY7C1414BV18 PRELIMINARY 36-Mbit QDR-II SRAM 2-Word Burst Architecture Features Functional Description • Separate Independent Read and Write data ports The CY7C1410BV18, CY7C1425BV18, CY7C1412BV18 and CY7C1414BV18 are 1.8V Synchronous Pipelined SRAMs,

CY7C1410AV18

Abstract: CY7C1412AV18 CY7C1414AV18 CY7C1425AV18
Contextual Info: CY7C1410AV18 CY7C1425AV18 CY7C1412AV18 CY7C1414AV18 36-Mbit QDR-II SRAM 2-Word Burst Architecture Features Functional Description • Separate Independent Read and Write data ports The CY7C1410AV18, CY7C1425AV18, CY7C1412AV18, and CY7C1414AV18 are 1.8V Synchronous Pipelined SRAMs,

Contextual Info: CY7C1410BV18 CY7C1425BV18 CY7C1412BV18 CY7C1414BV18 PRELIMINARY 36-Mbit QDR-II SRAM 2-Word Burst Architecture Features Functional Description • Separate Independent Read and Write data ports The CY7C1410BV18, CY7C1425BV18, CY7C1412BV18 and CY7C1414BV18 are 1.8V Synchronous Pipelined SRAMs,

IR 10e 3e

Contextual Info: CY7C1410AV18 CY7C1425AV18 CY7C1412AV18 CY7C1414AV18 36-Mbit QDR-II SRAM 2-Word Burst Architecture Features Functional Description • Separate Independent Read and Write data ports The CY7C1410AV18, CY7C1425AV18, CY7C1412AV18, and CY7C1414AV18 are 1.8V Synchronous Pipelined SRAMs,

CY7C1410AV18

Abstract: CY7C1412AV18 CY7C1414AV18 CY7C1425AV18
Contextual Info: CY7C1410AV18 CY7C1425AV18 CY7C1412AV18 CY7C1414AV18 36-Mbit QDR-II SRAM 2-Word Burst Architecture Features Functional Description • Separate Independent Read and Write data ports The CY7C1410AV18, CY7C1425AV18, CY7C1412AV18, and CY7C1414AV18 are 1.8V Synchronous Pipelined SRAMs,

ls404cb

Abstract: "Bandpass Filter" 50 hz
Contextual Info: 4 2E G ì » 7^2=1237 □035fl7b S C S - T H O M S O N S ISGTH s 6 S-THOMSON T ~ 7 9 -06-20 mo LS404 HIGH PERFORMANCE QUAD OPERATIONAL AMPLIFIERS • ■ ■ ■ ■ ■ SINGLE OR SPLIT SUPPLY OPERATION VERY LOW POWER CONSUMPTION SHORT CIRCUIT PROTECTION LOW DISTORTION, LOW NOISE

LS404CB

Abstract: 2RF01 LS404 LS404C LS404CD1 LS404D1 LS8404C
Contextual Info: 42E » £ r7 7^2=1237 □035fl7b S S C S -T H O M S O N ISGTH s 6 S-THOMSON T~79-06-20 LS404 mo HIGH PERFORMANCE QUAD OPERATIONAL AMPLIFIERS • ■ ■ ■ ■ ■ SINGLE OR SPLIT SUPPLY OPERATION VERY LOW POWER CONSUMPTION SHORT CIRCUIT PROTECTION LOW DISTORTION, LOW NOISE

Contextual Info: □PM DPS832V Dense-Pac Microsystems, I n a , CMOS SRAM VERSAPAC MODULE DESCRIPTION: The DPS832V is a 66-pin Pin Grid Array PGA consisting of four 8K X 8 SRAM devices in ceramic LC C packages surface mounted on a co-fired ceram ic substrate with m atching thermal

MN5906

Contextual Info: nsai M N 590 6 y _ _ M IC R O N E T W O R K S ^ 6-Bit, 50MHz CMOS FLASH A/D CONVERTER ^ IUB0 9001/Bi 2J001 DESCRIPTION FEATURES • 6-Bit Resolution Plus Overflow Bit • 50MHz typical Conversion Rate • Single +5V Operation • T/H Not Required • SO MHz min.

SM6322

Abstract: MSM6322 DD172 voice changer microphone 4MHZ oscillator XT MSM6322 SOP Voice changer IC mic PRE-AMPLIFIER with equalizer voice changer
Contextual Info: O K I Semiconductor MSM6322_ P ITC H C O N T R O L L S I FO R T H E S P E E C H SIG N A L G E N E R A L D E SC R IP TIO N The MSM6322 converts in realtime the pitch of the speech signal in a range of one octave upw ard or downward. Two pitch control methods can be selected.

Contextual Info: bl E bEMTflSS D OOEGMb? DT4 • M I T I MITSUBISHI LSIs MH1M09A0AJ - 6, - 7, - 8, -10/ MH1M09A0AJA- 6, - 7, - 8, -10 FAST PAGE MODE 1048576-WORD BY 9 - BIT DYNAMIC RAM MITSUBISHI MEMORY/ASIC DESCRIPTIO N The MH1M09A0AJ, J A is 1048576-word x 9- bit dynamic

Contextual Info: M X * C D M , I N C . . M X 6 1 3 Advance Information GLOBAL CALL PROGRESS DETECTOR Features • MX*COM MiXed Signal CMOS • Covers Worldwide Call Progress Frequencies 300Hz to 2,150Hz • 3 Volt <1 mA Requirement • Decodes Single or Modulated Tones * Telephone/Telecoms, Radio and Fax/Modem

3410 DVB

Abstract: 5-XX FAG 32 diode dvb-s2 i2c philips fag circuit BG1 d1 257 lnb schematic DVB-S2 demodulator
Contextual Info: ZL10038 Advanced Modulation Satellite Tuner Data Sheet Features November 2005 • Single-chip L band to zero IF quadrature down converter compliant with 1-45 Msps DVB-S2 • High dynamic range of -92 dBm to -10 dBm without RF attenuator or RSSI • High total composite power handling

DVB-S2 demodulator

Abstract: Single Chip dvb-s2 3410 DVB ZL10036 ZL10038 20 GHz PIN diode schematics c band satellite receiver DVB-S2 downconverter 400 xtal
Contextual Info: ZL10038 Advanced Modulation Satellite Tuner Data Sheet Features July 2004 • Single-chip L band to zero IF quadrature down converter compliant with 1-45 Msps DVB-S2 • High dynamic range of -92 dBm to -10 dBm without RF attenuator or RSSI • High total composite power handling

lnb schematic

Contextual Info: ZL10038 Advanced Modulation Satellite Tuner Data Sheet Features May 2004 • Single-chip L band to zero IF quadrature down converter compliant with 1-45 Msps DVB-S2 • High dynamic range of -92 dBm to -10 dBm without RF attenuator or RSSI • High total composite power handling