1024WORD Search Results

intel 2758 eprom

Abstract: MSM2128 MSM2758
Contextual Info: C - f2- * i - 003831 sem iconductor *MSM2758 MARCH 1980 | •i i 8,192-B IT 1024 X 8 UV ERASABLE PROM GENERAL DESCRIPTION FEATURES The Oki M SM2758 is a 8192-bit ultraviolet erasable and electrical program m able read-only memory organized as 1024words by 8-bits using O ki’s Floating Gate N-channei S ilicon Gate

MB7122E

Abstract: MB7122 mb7121 16as15 v024v MB7100 68Vt
Contextual Info: APR 2 1993 May 1990 Edition 4.0 FUJITSU DATASHEET'- MB7121E/H/L, MB7122E/H/Y/L PROGRAMMABLE SCHOTTKY 4096-BIT READ ONL Y MEMORY SCHOTTKY 4096-RT DEAP PROM 1024WORDS x 4BITS The Fujitsu MB7121 and MB7122 are high speed Schottky TTL electrically field programmable read only memories organized as 1024words by 4bits. With

MB7122

Abstract: MB7100 MB7122E LCC-20C-F02 MB712 MB7122E-W 1024-words eutec
Contextual Info: APR 2 1993 June 1990 Edition 3.0 FUJITSU DATA SHEET MB7122E-W/L-W PROGRAMMABLE SCHOTTKY 4096-BIT READ ONLY MEMORY SCHOTTKY 4096-BIT DEAP PROM 1024WORDS X 4BITS The Fujitsu MB7122-W is high speed Schottky TTL electrically field programmable read only memory organized as 1024words by 4bits. With three-state outputs on

SOP 8 200MIL

Abstract: serial flash 256Mb fast erase spi TM 1628 IC SOP Micron 512MB NOR FLASH HN29V1G91T-30 HN58C1001FPI-15 M5M51008DFP-70HI 256mb EEPROM Memory CSP-48 TSOP 28 SPI memory Package flash
Contextual Info: Renesas Memory General Catalog 2003.11 Renesas Memory General Catalog Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Keep safety first in your circuit designs! 1. Renesas Technology Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with

IBM "embedded dram"

Abstract: m5m4v4169 Intel 1103 DRAM Nintendo64 IBM98 toshiba fet databook dynamic memory controler MOSYS eDRAM "1t-sram" MoSys
Contextual Info: ABSTRACT MODERN DRAM ARCHITECTURES by Brian Thomas Davis Co-Chair: Assistant Professor Bruce Jacob Co-Chair: Professor Trevor Mudge Dynamic Random Access Memories DRAM are the dominant solid-state memory devices used for primary memories in the ubiquitous microprocessor systems of

MSM6389C

Abstract: SAS controller chip MSM6389CJS
Contextual Info: E2D0033-39-21 ¡ Semiconductor MSM6389C ¡ Semiconductor This version: MSM6389C Feb. 1999 Previous version: May. 1997 1,048,576-Word x 1-Bit Solid-State Recorder Data Register GENERAL DESCRIPTION The MSM6389C is a solid-state recorder data register in 1,048,576 words x 1 bit configuration.

MSM6596A

Abstract: MSM6388 MSM6389 MSM6588 SSOP30-P-56-0
Contextual Info: E2D0039-39-21 This version: Feb. 1999 MSM6596A-xxx Previous version: May. 1997 ¡ Semiconductor MSM6596A-xxx ¡ Semiconductor 2-Mbit Serial Voice ROM GENERAL DESCRIPTION The MSM6596A is the shorter-TAT processing version of the MSM6596. The MSM6596A is a serial voice ROM with a 1,048,576-word ¥ 1-bit ¥ 2-bank configuration.

HN58X2508FPIE

Abstract: HN58X2508I HN58X2508TIE HN58X2516FPIE HN58X2516I HN58X2516TIE
Contextual Info: HN58X2508I HN58X2516I Serial Peripheral Interface 8k EEPROM 1024-word x 8-bit 16k EEPROM (2048-word × 8-bit) Electrically Erasable and Programmable Read Only Memory REJ03C0222-0200 Rev.2.00 Aug.19.2004 Description HN58X25xxx Series is the Serial Peripheral Interface (SPI) EEPROM (Electrically Erasable and

Contextual Info: Fo r t une Semiconductor Corporation 富晶半導體股份有限公司 FS9168 8-bit MCU with 1k program ROM, 64-byte RAM, 1 R2F module and 3 x 13 LCD driver. Data Sheet TD-0410001 Rev. 1.2 This manual contains new product information. Fortune Semiconductor Corporation reserves the rights to

HN25088L

Abstract: HN25089L Hitachi Scans-001
Contextual Info: H N 2 5 8 8 L , H N 2 5 Ö 9 L 1024-word x 8-bit Programmable Read Only Memories The H IT A C H I H N 2 5 0 8 8 L and H N 2 5 0 8 9 L are lo w po w e r and high speed e le c tric a lly program m able, fu lly decoded T T L B ip o la r 8192 b it read o n ly m em ories organized as 1024 w ord s b y 8 bits w ith onc h ip address decoding and fo u r c h ip enable inputs.

high level block diagram for asynchronous FIFO

Abstract: DIP28-W-300 LH540202 LJH540202
Contextual Info: LH540202 CMOS 1024 X 9 Asynchronous FIFO FEATURES FUNCTIONAL DESCRIPTION • Fast Access Times: 15/20/25/35/50 ns The LH540202 is a FIFO First-In, First-Out memory device, based onfully-staticCMOSdual-portSRAM tech­ nology, capable of storing up to 1024 nine-bit words. It

TMS320C6713pyp

Abstract: SPRS186 TMS320C6713 ccfg C6713 SPRU190 TMS320C6000 TMS320C6713 TMS320C6713B TMS320c6713 hpi mcbsp
Contextual Info: TMS320C6713, TMS320C6713B Digital Signal Processors Silicon Errata C6713 Silicon Revision 1.1 C6713B Silicon Revision 2.0 SPRZ191G December 2002 Revised May 2004 Copyright  2004, Texas Instruments Incorporated TMS320C6713, TMS320C6713B Silicon Errata SPRZ191G

Contextual Info: 57C4502-50/65/80 High Density First-in First-out FIFO 1024x9 CMOS Memory cn ~>l O Advance Information DISTINCTIVE CHARACTERISTICS RAM based FIFO 1024x9 organization Cycle times of 65/80/100 nanoseconds Asynchronous and simultaneous writes and reads Low power consumption - 80 mA maximum

Contextual Info: Am27S35/Am27S37 8,192-Bit 1024x8 Bipolar Registered PROM with Programmable INITIALIZE Input Versatile programmable asynchronous or synchronous enable for simplified word expansion Buffered common INITIALIZE input either asynchronous (Am27S35) or synchronous (Am27S37)

Contextual Info: H I T A C H I / LOGIC/ARRAYS/MEN TS D Ë | 44=11,203 0010=135 b | ~ 92D H M I 0 0 4 7 4 , H M 1 4 7 4 F 10932 -^ T -4 6 -2 3 -0 8 1 0 2 4 - w o r d x 4 - b i t F u lly D e c o d e d R a n d o m A c c e s s M e m o r y The H M 100474 is a 1024-words x 4-bit, read/write, random access

Contextual Info: DOC BU-61590 ILC DATA DEVICE CORPORATION — MIL-STD-1553A/B & Me AIR BC/RT/MT, ADVANCED COMMUNICATION ENGINE ACE FEATURES DESCRIPTION DDC’s BU-61590 BC/RT/MT Universal Advanced C om m unication Engine (ACE) terminal comprises a complete integrated interface between a host

HD63183

Contextual Info: Under Development H D63185- D ocum ent Im age Com pression and Expansion Processor Enhanced DICEP-E DICEP-E is an LSI th a t perform s com pression (encoding) and expansion (decoding) of 2value d a ta used to rep resen t a docum ent image. It is positioned a t th e high en d of th e

HM 1211

Abstract: HM2110 HM2110-1 Jj-80
Contextual Info: H M 2 1 1 0 , H M 2 1 1 0 -1 1 0 2 4 - w o rd x 1 - b i t F u lly D e c o d e d R a n d o m A c c e s s M e m o ry The H M 21 10 Series item is an ECL compatible, 1024-word x 1-bit, read/write, random access memory developed for application to scratch pads, control and buffer memories, etc. which require high

HE8P1603P

Abstract: HE8P1603S P12W hxosc
Contextual Info: HE8P1603 HE8P1603 PRODUCT SPECIFICATION 1. GENERAL DESCRIPTION . 3 2. FEATURES . 3

S590

Abstract: S-29530A S-29590A S-29590ADPA S-29630A S-29690A S-29690ADPA S-29X90A S690
Contextual Info: Contents Features. 1 Pin Assignment . 1 Pin Functions . 1 Block Diagram. 2

SPH-002T-P0.5S

Abstract: motorolla processor DSP56000 DSP56300 DSP56307 DSP56L307
Contextual Info: Order Number EB361/D: Rev. 1, 3/2001 MOTOROLA Semiconductor Products Sector Engineering Bulletin Functional Differences Between the Motorola DSP56307 and DSP56L307 The DSP56307 and DSP56L307, two members of the Motorola DSP56300 family of programmable digital signal processors

SN74ACT8994

Abstract: PIN CONFIGURATION pci 32 bit 5 v
Contextual Info: SN74ACT8994 DIGITAL BUS MONITOR IEEE STD 1149.1 JTAG SCAN-CONTROLLED LOGIC/SIGNATURE ANALYZER SCAS196E – JULY 1990 – REVISED DECEMBER 1996 D D D D D D D Member of the Texas Instruments SCOPE  Family of Testability Products Compatible With the IEEE Standard

ic 2114

Abstract: 2114 static ram memory ic 2114 pin out
Contextual Info: SEMI 2114 STATIC, TTL IN/OUT 1024x4 N-MOS RAM's FEATURES • 1024 words x 4 bits • Three access times 200, 300, and 450 nsec • Low operating power — 175 mW typical • Common output bus • Three-state output drivers • Fully STATIC — no clock or refresh

BR24L04

Abstract: BR24L08 BR24L08FJ-W BR24L08FVM-W BR24L08FV-W BR24L08F-W BR24L08-W BR24L16
Contextual Info: BR24L08-W / BR24L08F-W / BR24L08FJ-W BR24L08FV-W / BR24L08FVM-W Memory ICs 1024x8 bit electrically erasable PROM BR24L08-W / BR24L08F-W / BR24L08FJ-W / BR24L08FV-W / BR24L08FVM-W The BR24L08-W series is 2-wire I2C BUS type serial EEPROMs which are electrically programmable.