10148 Search Results

Contextual Info: * SY10/100/101480-6 SY10/100/101480-8 SY10/100/101480-10 16K x 1 EC L RAM SYNERGY S E M IC O N D U C TO R DESCRIPTION FEATURES • Address access time, tAA: 6/8/10ns max. ■ Chip select access time, tAC: The Synergy SY10/100/101480 are 16384-bit Random Access Memories RAMs , designed with advanced Emitter

vhdl code for branch metric unit

Abstract: processor control unit vhdl code processor control unit vhdl code download vhdl coding for hamming code branch metric vhdl code 16 bit processor hamming decoder vhdl code 5 to 32 decoder using 3 to 8 decoder vhdl code Radix selection unit radix 2 verilog
Contextual Info: VITERBI_DEC Viterbi Decoder January 10, 2000 Product Specification AllianceCORE Facts CSELT S.p.A Via G. Reiss Romoli, 274 I-10148 Torino, Italy Phone: +39 011 228 7165 Fax: +39 011 228 7003 E-mail: viplibrary@cselt.it URL: www.cselt.it Features • Supports Spartan, Spartan™-II, Virtex™, and

S435a

Abstract: C1467 SKY74038 SMV0550L V630ME03 51c33
Contextual Info: USER GUIDE SKY74038 Frequency Synthesizer Evaluation Board Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com 101483E • Skyworks Proprietary and Confidential information • Products and Product Information are Subject to Change Without Notice • October 10, 2005

lcd mp4

Abstract: 12mhz mp5 12mhz mp5 CRYSTAL DDR4 mb89051 FPT-64P-M09 LQFP-64 MB89F051 LC1 FH 43 al4142
Contextual Info: FUJITSU SEMICONDUCTOR CM25-10148-XE CONTROLLER MANUAL F2MC-8L 8 BIT MICRO CONTROLLER MB89051 Series HARDWARE MANUAL F2MC-8L 8 BIT MICRO CONTROLLER MB89051 Series HARDWARE MANUAL FUJITSU LIMITED PREFACE • Purpose of this document and intended reader The MB89051 Series products were developed as the general-purpose version of the F2MC-8L

Convolutional Encoder

Abstract: xilinx vhdl codes convolutional encoder source code X9064
Contextual Info: ac_cselt_conv_enc.fm Page 1 Wednesday, March 14, 2001 12:30 PM CONV_ENC Convolutional Encoder December 07, 2000 Product Specification AllianceCORE Facts Tilab Via G. Reiss Romoli, 274 10148 Torino, Italy Phone: +39 011 228 5659 Fax: +39 011 228 7140 E-mail: viplibrary@tilab.com

Contextual Info: 101484HF-4/4.5 Preliminary ECL I/O 4096-word x 4 bit Fully Decoded Random Access Memory Pin Arrangement Description The H M 101484H is ECL 100k com patible, 4096-w ord by 4-bit read/write random access memory developed for high speed systems such as scratch pads and control/buffer storage.

vhdl code for 8-bit parity generator

Abstract: vhdl code for 9 bit parity generator vhdl code for 8 bit parity generator vhdl code for 4 bit even parity generator cell phone vhdl 8 bit parity generator code block code error management, verilog source code DPRAM vhdl code it parity generator vhdl code for a 9 bit parity generator
Contextual Info: UTOPIA_L2_TX UTOPIA Level 2 PHY Side TX Interface January 10, 2000 Product Specification AllianceCORE Facts CSELT S.p.A Via G. Reiss Romoli, 274 I-10148 Torino, Italy Phone: +39 011 228 7165 Fax: +39 011 228 7003 E-mail: viplibrary@cselt.it URL: www.cselt.it

vhdl code scrambler

Abstract: scrambling design of scrambler and descrambler verilog code for implementation of des error correction code in vhdl vhdl code Linear block code Scrambler vhdl code for pseudo random sequence generator crc 16 verilog vhdl code CRC 32
Contextual Info: DSS Distributed Sample Scrambler January 10, 2000 Product Specification AllianceCORE Facts CSELT S.p.A Via G. Reiss Romoli, 274 I-10148 Torino, Italy Phone: +39 011 228 7165 Fax: +39 011 228 7003 E-mail: viplibrary@cselt.it URL: www.cselt.it Features • Supports Spartan, Spartan™-II, Virtex™, and

Contextual Info: Accessories Connectors and cables Female connector M8, 4-pin, angled Part number 10148328 Female connector M8, 4-pin, angled, 5 m cable Suitable for 1 www.baumer.com/motion 17/1/2012 Subject to modiication in technic and design. Errors and omissions excepted.

Contextual Info: H D 10148 6 4 -b it Random A ccess Mem ory The 10148 is a fast 64-word x 1-bit RAM. Bit selection is achieved by means of a 6-bit address, AO through A5. The active low chip selects and fast chip select access time allow easy memory expansion up to 256 words w ithout affecting

10D13

Contextual Info: 101484HF-4/4.5 Preliminary ECL I/O 4096-word x 4 bit Fully Decoded Random Access Memory Description Pin Arrangement T he H M 101484H is ECL 100k com p atib le, 40 9 6 -w o r d by 4 -b it read /w rite random a c ce ss memory developed for high speed systems such as

vhdl code for matrix multiplication

Abstract: VHDL code DCT vhdl code for inverse matrix vhdl code for transpose memory vhdl coding for pipeline matrix multiplication code in vhdl with testbench file verilog code for 8x8 matrix multiplication matrix multiplier Vhdl code idct vhdl code verilog code for matrix multiplication
Contextual Info: FIDCT Forward/Inverse Discrete Cosine Transform September 18, 2000 Product Specification AllianceCORE Facts CSELT S.p.A Via G. Reiss Romoli, 274 I-10148 Torino, Italy Phone: +39 011 228 5259 Fax: +39 011 228 5695 E-mail: viplibrary@cselt.it URL: www.cselt.it

Contextual Info: H D 10148 64-b it Random Access Memory The H D 10148 is a fast 64-w ord x 1-bit R AM . B it selection is achieved by means o f a 6 -b it address, inputs low is co n tro lle d by the WE in p u t. W ith WE low the chip is in the w rite mode- The o u tp u t

HD10148

Abstract: ve32
Contextual Info: H D 10148 6 4 - b i t R and o m A c c e s s M em o ry inputs low is controlled by the W E in put. W ith The H D 1 0 1 4 8 is a fast 64-w ord x 1-bit R A M . Bit W E low the chip is in the w rite mode- The ou tp ut is lo w and the data present at Din is stored at the

DPRAM

Abstract: vhdl code for 4 bit even parity generator 4 bit gray code counter VHDL
Contextual Info: UTOPIA_L2_RX UTOPIA Level 2 PHY Side RX Interface Januaryk 10, 2000 Product Specification AllianceCORE Facts CSELT S.p.A Via G. Reiss Romoli, 274 I-10148 Torino, Italy Phone: +39 011 228 7165 Fax: +39 011 228 7003 E-mail: viplibrary@cselt.it URL: www.cselt.it

SY101484-4

Abstract: SY10484-5CCF SY101484-6FCF S2811
Contextual Info: * SYNERGY SY10484-4/5/6 SY100484-4/5/6 101484-4/5/6 4K x 4 ECL RAM S E M IC O N D U C TO R DESCRIPTION FEATURES The Synergy SY10/100/101484 are 16384-bit Random Access Memories RAMs , designed with advanced Emitter Coupled Logic (ECL) circuitry. The devices are organized

design of scrambler and descrambler

Abstract: vhdl code scrambler verilog code for implementation of des error correction code in vhdl vhdl code for phase shift Descrambler vhdl code for scrambler descrambler cell phone vhdl code for pseudo random sequence generator crc 16 verilog
Contextual Info: DSD Distributed Sample Descrambler January 10, 2000 Product Specification AllianceCORE Facts CSELT S.p.A Via G. Reiss Romoli, 274 I-10148 Torino, Italy Phone: +39 011 228 7165 Fax: +39 011 228 7003 E-mail: viplibrary@cselt.it URL: www.cselt.it Features

Contextual Info: * SY100480-6 101480-6 16K x 1 ECL RAM SYNERGY SEMICONDUCTOR DESCRIPTION FEATURES The Synergy SY100/101480 are 16384-bit Random Access Memories RAMs , designed with advanced Emitter Coupled Logic (ECL) circuitry. The SY100/101480 are organized as 16384-words-by-1-bit, meet the standard 100K

10140

Abstract: SETD 10151 ECL 10000 10148
Contextual Info: s ig n o t iC B - 3 0 to + 8 5 10140 10148 10151 C C E R D IP ^ A D V A N C E D IN F O R M A T IO N DIGITAL 10,000 ECL SERIES d e s c r ip t io n Tta 10140, 1 0 1 4 8 and 1 0 1 5 ! are 6 4 Bit E C L Random Access Memories R A M 's organised as 6 4 w ords with. 1 b.

101490

Abstract: 100A484 100A484S8 101A48
Contextual Info: ID T 10/1 0 0 /1 0 1 4 8 4 D a ta B o o k B, S e c tio n 5.1 , P a g e 8 AC ELECTRICAL CHARACTERISTICS Over the AC Operating Range Test Symbol Parameter*1) 10484S8 100484S8 101484S8 10484S7 100484S7 101484S7 10484S10 100484S10 101484S10 10484S15 100484S15

8a2c

Contextual Info: M OTOROLA 64 X 1 BIT RANDOM ACCESS MEMORY MECL The M C M 10148 is a fast 64-w ord X 1 -bit RAM. Bit selection is achieved by means of a 6-bit address, AO through A5. The active-low chip selects and fast chip select access tim e allow easy m em ory expansion up to 256 w ords w ith o u t affecti ng system perform ance. The operating mode CS inputs low

SY100480-8DCF

Contextual Info: SY N E R G Y S E M I C O N D U C T O R « S7E » • TDD13Ö1 0GGQD27 22^ SY10480-8/10 16K X 1 ECL RAM SYNERGY SY100480-8/10 SEMICONDUCTOR 101480-8/10 DESCRIPTION FEATURES The Synergy SY10/100/101480 are 16384-bit Random Access Memories RAMs , designed with advanced Emitter

vhdl code 16 bit LFSR

Abstract: vhdl code 8 bit LFSR vhdl code 4 bit LFSR vhdl code 10 bit LFSR vhdl code 16 bit LFSR with VHDL simulation output verilog code 8 bit LFSR verilog code 16 bit LFSR verilog code 32 bit LFSR verilog code 5 bit LFSR pseudo random generator
Contextual Info: Channel January 10, 2000 Product Specification AllianceCORE Facts CSELT S.p.A Via G. Reiss Romoli, 274 I-10148 Torino, Italy Phone: +39 011 228 7165 Fax: +39 011 228 7003 E-mail: viplibrary@cselt.it URL: www.cselt.it Features • Supports Spartan, Spartan™-II, Virtex™, and

Shared resource arbitration

Contextual Info: Arbiter January 10, 2000 Product Specification AllianceCORE Facts CSELT S.p.A Via G. Reiss Romoli, 274 I-10148 Torino, Italy Phone: +39 011 228 7165 Fax: +39 011 228 7003 E-mail: viplibrary@cselt.it URL: www.cselt.it Features • Supports Spartan, Spartan™-II, Virtex™, and