100PINTQFP Search Results

SOP 8 200MIL

Abstract: serial flash 256Mb fast erase spi TM 1628 IC SOP Micron 512MB NOR FLASH HN29V1G91T-30 HN58C1001FPI-15 M5M51008DFP-70HI 256mb EEPROM Memory CSP-48 TSOP 28 SPI memory Package flash
Contextual Info: Renesas Memory General Catalog 2003.11 Renesas Memory General Catalog Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Keep safety first in your circuit designs! 1. Renesas Technology Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with

Contextual Info: [s e m ic o n d u c t o r AP9B132 ADVANCED INFORMATION 32K x 32,3.3 V Pipelined Synchronous Burst Mode SRAM • • • • Features • • • • • • • • • • • • Fast access times: 4 .5 ,5 ,6, 7, and 8 ns Fast OE access times: 5 and 6 ns

Contextual Info: PRELIMINARY C Y 7C 374i UltraLogic 128-Macrocell Flash CPLD Features • • • • 128 macrocells in eight logic blocks 64 I/O pins 5 dedicated inputs including 4 clock pins In-System Reprogrammable ISR™ Flash technology — JTAG interface • Bus Hold capabilities on all l/Os and dedicated inputs

71V2578

Contextual Info: 128K X 36, 256K X 18 3.3V Synchronous SRAMs 2.5V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Features ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ IDT71V2576S IDT71V2578S IDT71V2576SA IDT71V2578SA Description 128K x 36, 256K x 18 memory configurations

INTEGRATED DEVICE TECHNOLOGY 71V432

Contextual Info: 32K x 32 CacheRAM 3.3V Synchronous SRAM Burst Counter Single Cycle Deselect Features ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ IDT71V432 processor interfaces. The pipelined burst architecture provides costeffective 3-1-1-1 secondary cache performance for processors up to

PLSI 1016-60LJ

Abstract: PAL 007 pioneer pal16r8 programming algorithm PAL 008 pioneer lattice 1016-60LJ ISP Engineering Kit - Model 100 PLSI-2064-80LJ GAL16v8 programmer schematic GAL programming Guide ispLSI 2064-80LT
Contextual Info: Lattice Semiconductor Data Book 1996 Click on one of the following choices: • Table of Contents • Data Book Updates & New Products • Go to Main Menu 1996 Lattice Semiconductor Corporation. All rights reserved. ispLSI and pLSI Product Index Pins Density

IDT71V632

Abstract: sram with address counter
Contextual Info: 64K x 32 3.3V Synchronous SRAM Pipelined Outputs Burst Counter, Single Cycle Deselect Features ◆ ◆ ◆ ◆ ◆ ◆ ◆ with full support of the Pentium and PowerPC™ processor interfaces. The pipelined burst architecture provides cost-effective 3-1-1-1 secondary cache performance for processors up to 117MHz.

IDT71V633

Contextual Info: 64K x 32 3.3V Synchronous SRAM Flow-Through Outputs Burst Counter, Single Cycle Deselect IDT71V633 Features ◆ ◆ ◆ ◆ ◆ ◆ ◆ 64K x 32 memory configuration Supports high performance system speed Commercial: — 11 11ns Clock-to-Data Access 50 MHz

IDT71V433

Abstract: pin diagram for core i3 processor
Contextual Info: 32K x 32 3.3V Synchronous SRAM Flow-Through Outputs IDT71V433 Features ◆ ◆ ◆ ◆ ◆ ◆ 32K x 32 memory configuration Supports high performance system speed: Commercial and Industrial: — 11 11ns Clock-to-Data Access 50MHz — 12 12ns Clock-to-Data Access (50MHz)

Contextual Info: M A X 7000A Programmable Logic Device Family January 1 9 9 8 . v er. 1 Data Sheet AX 7DG0 Features. Prelim inary Information • ■ ■ Formerly known as Michelangelo devices High-performance CMOS EEPROM-based programmable logic devices PLDs built on second-generation M ultiple Array Matrix

M5281

Abstract: 71V3558S 71V3556S 71V3558SA
Contextual Info: 128K x 36, 256K x 18 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter Pipelined Outputs Description Features ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ IDT71V3556S/XS IDT71V3558S/XS IDT71V3556SA/XSA IDT71V3558SA/XSA The IDT71V3556/58 are 3.3V high-speed 4,718,592-bit 4.5 Megabit synchronous SRAMS. They are designed to eliminate dead bus

71V2578

Contextual Info: 128K X 36, 256K X 18 3.3V Synchronous SRAMs 2.5V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Features ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ Preliminary IDT71V2576 IDT71V2578 Description 128K x 36, 256K x 18 memory configurations Supports high system speed:

71V3577

Contextual Info: 128K X 36, 256K X 18 3.3V Synchronous SRAMs 3.3V I/O, Flow-Through Outputs Burst Counter, Single Cycle Deselect Description Features ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ Preliminary IDT71V3577 IDT71V3579 The IDT71V3577/79 are high-speed SRAMs organized as 128K x 36/256K x 18. The IDT71V3577/79 SRAMs contain write, data,

71V3577

Contextual Info: 128K X 36, 256K X 18 3.3V Synchronous SRAMs 3.3V I/O, Flow-Through Outputs Burst Counter, Single Cycle Deselect Description Features ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ Preliminary IDT71V3577 IDT71V3579 The IDT71V3577/79 are high-speed SRAMs organized as 128K x 36/256K x 18. The IDT71V3577/79 SRAMs contain write, data,

Contextual Info: 64K x 32 3.3V Synchronous SRAM Pipelined Outputs Burst Counter, Single Cycle Deselect Features ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ IDT71V632 with full support of the Pentium and PowerPC™ processor interfaces. The pipelined burst architecture provides cost-effective 3-1-1-1 secondary cache performance for processors up to 117MHz.

S3F82F5

Abstract: S3C828B FM24653 ISO-14001 F8289 S3C82F5 S3F80M4
Contextual Info: S3C82F5/F82F5 8-BIT CMOS MICROCONTROLLERS USER'S MANUAL Revision 1.10 Important Notice The information in this publication has been carefully checked and is believed to be entirely accurate at the time of publication. Samsung assumes no responsibility, however, for possible errors or

IDT71V2576

Abstract: IDT71V2578 max3035 71V2578
Contextual Info: 128K X 36, 256K X 18 3.3V Synchronous SRAMs 2.5V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Features ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ IDT71V2576 IDT71V2578 Description 128K x 36, 256K x 18 memory configurations Supports high system speed:

IDT71V633

Contextual Info: 64K x 32 3.3V Synchronous SRAM Flow-Through Outputs Burst Counter, Single Cycle Deselect IDT71V633 Features ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ tecture provides cost-effective 2-1-1-1 performance for processors up to 50 MHz. The IDT71V633 SRAM contains write, data-input, address and control

IDT71V2576

Abstract: IDT71V2578 71V2578
Contextual Info: 128K X 36, 256K X 18 3.3V Synchronous SRAMs 2.5V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Features ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ Preliminary IDT71V2576 IDT71V2578 Description 128K x 36, 256K x 18 memory configurations Supports high system speed:

IDT71V3577

Abstract: IDT71V3579
Contextual Info: 128K X 36, 256K X 18 3.3V Synchronous SRAMs 3.3V I/O, Flow-Through Outputs Burst Counter, Single Cycle Deselect Description Features ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ Preliminary IDT71V3577 IDT71V3579 The IDT71V3577/79 are high-speed SRAMs organized as 128K x 36/256K x 18. The IDT71V3577/79 SRAMs contain write, data,

Contextual Info: SSRAM AS5SP1M18 Plastic Encapsulated Microcircuit 18Mb, 1M x 18 Synchronous SRAM Pipelined Burst, Single Cycle Deselect FEATURES • -55oC to +125oC Operation • Supports bus operation up to 200 MHz • Available speed grades are 200 and 166 MHz • Registered inputs and outputs for pipelined operation

Contextual Info: 21-S3-C831B/P831B-062003 USER'S MANUAL S3C831B/P831B 8-Bit CMOS Microcontroller Revision 1 S3C831B/P831B 1 PRODUCT OVERVIEW PRODUCT OVERVIEW S3C8-SERIES MICROCONTROLLERS Samsung's S3C8 series of 8-bit single-chip CMOS microcontrollers offers a fast and efficient CPU, a wide range

CY7C1367A

Abstract: GVT71512C18 4947a
Contextual Info: CY7C1366A/GVT71256C36 CY7C1367A/GVT71512C18 256K x 36/512K x 18 Synchronous Pipelined SRAM Features 18 SRAM cells with advanced synchronous peripheral circuitry and a 2-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a

C3157

Contextual Info: fax id: 6139 CY7C374Ì :/ C Y P R E S S UltraLogic 128-Macrocell Flash CPLD Features Functional Description • 128 macrocells in eight logic blocks • 64 I/O pins • 5 dedicated inputs including 4 clock pins The CY7C374i is an In-System Reprogrammable Complex