100E195 Search Results
100E195 Price and Stock
onsemi MC100E195FNR2G- Tape and Reel (Alt: MC100E195FNR2G) |
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MC100E195FNR2G | Tape & Reel | 500 |
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MC100E195FNR2G | 4,371 |
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onsemi MC100E195FNR2Active Programmable Delay Line 1-IN 0.02ns ABS 4.03ns MAX 28-Pin PLCC T/R |
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MC100E195FNR2 | 262 |
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Motorola Semiconductor Products MC100E195FNActive Programmable Delay Line 1-IN 0.02ns ABS 4.03ns MAX 28-Pin PLCC Rail |
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MC100E195FN | 7 | 1 |
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| MC100E195FN | 4 |
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onsemi MC100E195FNG5V ECL Programmable Delay Chip |
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MC100E195FNG | 1,819 | 1 |
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Micrel Inc SY100E195JCDelay Line IC Programmable 1.39ns 28-LCC |
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| Distributors | Part | Package | Stock | Lead Time | Min Order Qty | Price | Buy | ||||
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SY100E195JC | 9,530 | 1 |
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100E195 Datasheets Context Search
| Catalog Datasheet | Type | Document Tags | |
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pdc 140
Abstract: DL140 E195 MC100E195 MC10E195
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mc10e195mc100e195mc10e/100e195dl140+3 | |
DL140
Abstract: E195 MC100E195 MC10E195
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mc10e195/dmc10e195mc100e195mc10e/100e195+2 | |
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Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA MC10E195 M 100E195 Program m able Delay Chip The MC10E/100E195 is a programmable delay chip PDC designed primarily for clock de-skewing and timing adjustment. It provides variable delay ot a differential ECL input transition. |
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mc10e195c100e195mc10e/100e195dl140 | |
E195
Abstract: SY100E195 SY10E195 SY10E195JC
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sy10e195sy100e195sy10/100e195m9999-032006+2 | |
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Contextual Info: MOTOROLA Order this document by MC10E195/D SEMICONDUCTOR TECHNICAL DATA M C 10E195 M C 100E195 Program m able D elay Chip The MC1OE/100E195 is a programmable delay chip PDC designed primarily for clock de-skewing and timing adjustment. It provides variable |
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mc10e195/dmc1oe/100e195 | |
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Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA MC10E195 M 100E195 Programmable Delay Chip The MC10E/100E195 is a programmable delay chip PDC designed primarily for clock de-skewing and timing adjustment. It provides variable delay of a differential ECL input transition. |
OCR Scan |
mc10e/100e195dl140 | |
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Contextual Info: * PROGRAMMABLE DELAY CHI P SYNERGY SEMICONDUCTOR I FEATURES_ • ■ Up to 2ns delay range ■ 20ps/digital step resolution ■ >1 GHz bandwidth ■ On-chip cascade circuitry ■ ESD protection of 2000V ■ Fully compatible with Motorola MC10E/100E195 |
OCR Scan |
sy10e195sy100e19520ps/digitalmc10e/100e195+1 | |
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Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA M C10E195 100E195 Programmable Delay Chip The MC10E/100E195 is a programmable delay chip PDC designed primarily for clock de-skewing and timing adjustment. It provides variable delay of a differential ECL Input transition. |
OCR Scan |
c10e195mc100e195mc10e/100e195dl140 | |
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Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA MC10E195 100E195 Programmable Delay Chip The MC10E/100E195 is a programmable delay chip PDC designed primarily for clock de-skewing and timing adjustment. It provides variable delay of a differential ECL input transition. |
OCR Scan |
mc10e195mc100e195mc10e/100e1953b7252+1 | |
TRANSISTOR D 1765 720
Abstract: 100E195 E195 MC100E195 MC10E195
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mc10e195mc100e195mc10e/100e195mc10e195/d+3 | |
E195
Abstract: SY100E195 SY100E195JC SY10E195 SY10E195JC SY10E195JCTR
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sy10e195sy100e19520ps/digitalmc10e/100e195+6 | |
E195
Abstract: MC100E195 MC100E195FN MC100E195FNR2 MC10E195 MC10E195FN MC10E195FNR2
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mc10e195mc100e195mc10e/100e195r14525+6 | |
3870Contextual Info: MC10E195, 100E195 5V ECL Programmable Delay Chip The MC10E/100E195 is a programmable delay chip PDC designed primarily for clock de-skewing and timing adjustment. It provides variable delay of a differential ECL input transition. The delay section consists of a chain of gates organized as shown in |
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mc10e195mc100e195mc10e/100e195brd8011/d+5 | |
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Contextual Info: MC10E195, 100E195 5V ECL Programmable Delay Chip The MC10E/100E195 is a programmable delay chip PDC designed primarily for clock de-skewing and timing adjustment. It provides variable delay of a differential ECL input transition. The delay section consists of a chain of gates organized as shown in |
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mc10e195mc100e195mc10e/100e195mc10e195/d | |
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ic 1240 equivalent ics
Abstract: digital clock using logic gates 1-BIT D Latch D7 120 en 4020 TRANSISTOR D 1765 720 BUS BAR specification marking code onsemi Diode A6 MC100E195 pecl logic voltage levels
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mc10e195mc100e195mc10e/100e195mc10e195/d+9 | |
100E195
Abstract: E195 MC100E195 MC10E195
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mc10e195mc100e195mc10e/100e195mc10e195/d+2 | |
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Contextual Info: * PROGRAMMABLE DELAY CHIP SYNERGY SEMICONDUCTOR FEATURES DESCRIPTION Up to 2ns delay range ~20ps/digital step resolution >1GHz bandwidth On-chip cascade circuitry ESD protection of 2000V Fully compatible with Motorola MC10E/100E195 PIN CONFIGURATION N CO T |
OCR Scan |
20ps/digitalmc10e/100e195sy10e195sy100e195+3 | |
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Contextual Info: w Y 3? W >R DESCRIPTION • Up to 2ns delay range ■ Extended 100E V ee range of -4 .2 V to -5 .5 V ■ =20ps/digitai step resolution ■ >1 GHz bandwidth ■ On-chip cascade circuitry ■ 75Kki2 input pulldown resistor ■ Fully com patible with M otorola MC10E/100E195 |
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y10e19520ps/digitai75kki2mc10e/100e195+6 | |
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Contextual Info: bfiE D MOTOROLA • SEMICONDUCTOR bBb7ES5 OOTM'ÌVM EÔG m o m MOTOROLA SC LOÙIC I TECHNICAL DATA MC10E195 100E195 Programmable Delay Chip The MC10E/100E195 is a programmable delay chip (PDC) designed primarily for clock de-skewlng and timing adjustment. It provides variable |
OCR Scan |
mc10e195mc100e195mc10e/100e195 | |
TRANSISTOR D 1765 720
Abstract: E195 MC100E195 MC100E195FN MC100E195FNR2 MC10E195 MC10E195FN MC10E195FNR2
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mc10e195mc100e195mc10e/100e195r14525+7 | |
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Contextual Info: MOTOROLA O rder this docum ent by M C10E195/D SEMICONDUCTOR TECHNICAL DATA MC10E195 100E195 Programmable Delay Chip The MC10E/100E195 is a programmable delay chip PDC designed primarily for clock de-skewing and timing adjustment. It provides variable delay of a differential ECL input transition. |
OCR Scan |
c10e195/dmc10e195mc100e195mc10e/100e195 | |
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Contextual Info: MC10E195, 100E195 5V ECL Programmable Delay Chip Description The MC10E/100E195 is a programmable delay chip PDC designed primarily for clock de-skewing and timing adjustment. It provides variable delay of a differential ECL input transition. The delay section consists of a chain of gates organized as shown in |
Original |
mc10e195mc100e195mc10e/100e195mc10e195/d | |
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Contextual Info: *SYNERGY PR O G R A M M A B LE DELAY CHIP SEMICONDUCTOR FEATURES Clockworks SY10E195 100E195 DESCRIPTION Up to 2ns delay range =£Ops/digital step resolution >1GHz bandwidth On-chip cascade circuitry ESD protection of 2000V Fully compatible with Motorola MC10E/100E195 |
OCR Scan |
sy10e195sy100e195mc10e/100e19510/100e+4 | |
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Contextual Info: * PROGRAMMABLE DELAY CHIP SYNERGY SEM IC O N D U C TO R FEATURES • ■ C lo c k w o r k s ' SY10E195 S Y 10Q E 195 DESCRIPTION Up to 2ns d e la y range 2 0 p s /d ig ita l s te p re s o lu tio n ■ >1 GHz b a n d w id th ■ O n -c h ip c a sca d e c irc u itry |
OCR Scan |
sy10e19510e/100e195sy10/100e195sy100e195+3 | |