0XN115 Search Results

Contextual Info: XRT86VX38A 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION JULY 2013 REV. 1.0.0 GENERAL DESCRIPTION The XRT86VX38A is an eight-channel 1.544 Mbit/s or 2.048 Mbit/s DS1/E1/J1 framer and Long-haul/Shorthual LIU integrated solution featuring R3 technology

TR54016

Abstract: XRT86L38 XRT86VL34 XRT86VL34IB PIN26
Contextual Info: XRT86VL34 QUAD T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION JANUARY 2007 REV. V1.2.0 GENERAL DESCRIPTION The XRT86VL34 is a four-channel 1.544 Mbit/s or 2.048 Mbit/s DS1/E1/J1 framer and LIU integrated solution featuring R3 technology Relayless, Reconfigurable, Redundancy .

DMO 565 R

Abstract: dmo 465 Twelve NC Code
Contextual Info: xr XRT86L34 PRELIMINARY QUAD T1/E1/J1 FRAMER/LIU COMBO NOVEMBER 2004 REV. P1.1.6 GENERAL DESCRIPTION The XRT86L34 is a four-channel 1.544 Mbit/s or 2.048 Mbit/s DS1/E1/J1 framer and LIU integrated solution featuring R3 technology Relayless, Reconfigurable, Redundancy .

AIS-16

Contextual Info: XRT86SH328 VOYAGER - E1 FRAMER + LIU REGISTER DESCRIPTION MAY 2008 REV. 1.0.0 GENERAL DESCRIPTION The XRT86SH328 has a total of 42 independent E1 framers or 56 independent framers for T1 . This Voyager Device maps 21 E1 payloads up to STS-3/ STM-1. The purpose of the 42 framers is to allow

led cross reference

Abstract: XRT94L33 0x0382 0x1151 GR-253-CORE XRT94L33IB 0X176C 0x1738
Contextual Info: XRT94L33 333-C C H A N N E L D S E S T S T O S T S S T M M A P P E R A T M R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S-111 T TO OS ST TS S-333///S ST TM M-111 M MA AP PP PE ER R ––– A AT TM MR RE EG GIIIS ST TE ER RS S March 2007

CHN 648

Abstract: chn 542 CHN 612 diode CHN 552 CHN 628 CHN 522 CHN 632 chn 637 chn 621 CHN 631
Contextual Info: XRT86L38 PRELIMINARY PRELIMINARY OCTAL T1/E1/J1 FRAMER/LIU COMBO JUNE 2004 REV. P1.1.5 GENERAL DESCRIPTION The XRT86L38 is an eight-channel 1.544 Mbit/s or 2.048 Mbit/s DS1/E1/J1 framer and LIU integrated solution featuring R3 technology Relayless, Reconfigurable, Redundancy . The physical interface is optimized with internal impedance, and with the patented pad structure, the XRT86L38 provides protection

SLC96

Abstract: SLC-96 hdlc XRT86VL3X
Contextual Info: TAN-062 REV. 1.00 APPLICATION NOTE - PROCESSING HDLC MESSAGES TAN-062 Application Note Processing HDLC Messages XRT86VL3x DS-1/E1 Framer + LIU Combo 1 TAN-062 APPLICATION NOTE - PROCESSING HDLC MESSAGES REV. 1.00 TABLE OF CONTENTS 1.0 INTRODUCTION . 2

TR54016

Abstract: XRT86VX38
Contextual Info: XRT86VX38 8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION 2011 REV. 1.0.3 GENERAL DESCRIPTION The XRT86VX38 is an eight-channel 1.544 Mbit/s or 2.048 Mbit/s DS1/E1/J1 framer and Long-haul/Shorthual LIU integrated solution featuring R3 technology

CHN 612 diode

Abstract: CHN 545 CHN 648 chn 542 CHN 519 ST chn 624 CHN 507 SCR PIN CONFIGURATION CHN 035 CHN 522 CHN 535
Contextual Info: áç XRT86L38 PRELIMINARY PRELIMINARY OCTAL T1/E1/J1 FRAMER/LIU COMBO AUGUST 2004 REV. P1.1.6 GENERAL DESCRIPTION The XRT86L38 is an eight-channel 1.544 Mbit/s or 2.048 Mbit/s DS1/E1/J1 framer and LIU integrated solution featuring R3 technology Relayless, Reconfigurable, Redundancy . The physical interface is optimized with internal impedance, and with the patented pad structure, the XRT86L38 provides protection

dmo 565 r

Abstract: CHN 522 chn 542 chn 621 CHN 616 CHN 507 chn 638 chn 537 chn 543 CHN 618
Contextual Info: xr XRT86VL32 PRELIMINARY PRELIMINARY DUAL T1/E1/J1 FRAMER/LIU COMBO SEPTEMBER 2004 REV. P1.0.1 GENERAL DESCRIPTION The XRT86VL32 is a two-channel 1.544 Mbit/s or 2.048 Mbit/s DS1/E1/J1 framer and LIU integrated solution featuring R3 technology Relayless, Reconfigurable, Redundancy . The physical interface is optimized with internal impedance, and with the patented pad structure, the XRT86VL32 provides protection

xn300

Abstract: GR-253 GR-499-CORE XRT79L73 XRT79L73IB 0X0513
Contextual Info: PRELIMINARY XRT79L73 3 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC JUNE 2004 REGISTER MANUAL The XRT79L73 is a three channel, ATM UNI/PPP Physical Layer Processor with integrated DS3/E3 framing controllers and Line Interface Units with Jitter Attenuators that are designed to support ATM direct

Contextual Info: XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION JANUARY 2007 REV. V1.2.0 GENERAL DESCRIPTION The XRT86VL38 is an eight-channel 1.544 Mbit/s or 2.048 Mbit/s DS1/E1/J1 framer and LIU integrated solution featuring R3 technology Relayless,

GR-253-CORE

Abstract: XRT94L33 XRT94L33IB led cross reference 0x0106 0x1950 574 91 256 Sts.1
Contextual Info: XRT94L33 333-C C H A N N E L D S E S T S T O S T S S T M M A P P E R S O N E T R E G S T E R S CH HA AN NN NE EL LD DS S333///E E333///S ST TS S-111 T TO OS ST TS S-333///S ST TM M-111 M MA AP PP PE ER R ––– S SO ON NE ET TR RE EG GIIIS ST TE

framer E1

Abstract: TR54016 XRT86VL38 XRT86VL38IB XRT86VL38IB484
Contextual Info: XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION APRIL 2007 REV. V1.2.1 GENERAL DESCRIPTION The XRT86VL38 is an eight-channel 1.544 Mbit/s or 2.048 Mbit/s DS1/E1/J1 framer and LIU integrated solution featuring R3 technology Relayless, Reconfigurable, Redundancy . The physical interface

Contextual Info: xr XRT86VL34 PRELIMINARY QUAD T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION JULY 2005 REV. P1.0.5 GENERAL DESCRIPTION The XRT86VL34 is a four-channel 1.544 Mbit/s or 2.048 Mbit/s DS1/E1/J1 framer and LIU integrated solution featuring R3 technology Relayless,

CHN G4 309

Abstract: 40 serice free DMO 565 R CHN 932
Contextual Info: xr XRT86L38 PRELIMINARY OCTAL T1/E1/J1 FRAMER/LIU COMBO JANUARY 2005 REV. P1.1.7 GENERAL DESCRIPTION The XRT86L38 is an eight-channel 1.544 Mbit/s or 2.048 Mbit/s DS1/E1/J1 framer and LIU integrated solution featuring R3 technology Relayless, Reconfigurable, Redundancy .

Contextual Info: XRT86SH328 PRELIMINARY VOYAGER - E1 FRAMER + LIU REGISTER DESCRIPTION AUGUST 2007 REV. P1.0.0 GENERAL DESCRIPTION The XRT86SH328 has a total of 42 independent E1 framers or 56 independent framers for T1 . This Voyager Device maps 21 E1 payloads up to STS-3/

chn 542

Contextual Info: xr XRT86VL32 PRELIMINARY DUAL T1/E1/J1 FRAMER/LIU COMBO FEBRUARY 2005 REV. P1.0.3 GENERAL DESCRIPTION The XRT86VL32 is a two-channel 1.544 Mbit/s or 2.048 Mbit/s DS1/E1/J1 framer and LIU integrated solution featuring R3 technology Relayless, Reconfigurable, Redundancy .

Contextual Info: XRT86SH328 VOYAGER - T1 FRAMER + LIU REGISTER DESCRIPTION 2010 REV. 2.0.0 GENERAL DESCRIPTION The XRT86SH328 has a total of 56 independent T1 framers or 42 independent framers for E1 . This Voyager Device maps 28 T1 payloads up to STS-3/ STM-1. The purpose of the 56 framers is to allow

DMO 565 R

Abstract: chn 631 CHN 534 CHN 633 diode ST chn 624 TR54016 XRT84V24 XRT86L34 XRT86L34IB E1 frame
Contextual Info: xr XRT86L34 PRELIMINARY QUAD T1/E1/J1 FRAMER/LIU COMBO DECEMBER 2004 REV. P1.1.7 GENERAL DESCRIPTION The XRT86L34 is a four-channel 1.544 Mbit/s or 2.048 Mbit/s DS1/E1/J1 framer and LIU integrated solution featuring R3 technology Relayless, Reconfigurable, Redundancy .

LED VIPER

Abstract: VIPER IC AU-AIS GI 312 diode transistor st 431 SDH 209 sf 118 d SF 119 D viper 504 VIPer Design Software
Contextual Info: XRT94L31 333-C C H A N N E L D S E S T S T O S T S S T M M A P P E R S D H R E G S T E R M A P CH HA AN NN NE EL LD DS S333///E E333///S ST TS S-111 T TO OS ST TS S-333///S ST TM M-111 M MA AP PP PE ER R ––– S SD DH HR RE EG GIIIS ST TE ER RM

atm receiver multi bit error header

Abstract: GR-253 GR-499-CORE XRT79L72 XRT79L72IB G832
Contextual Info: PRELIMINARY XRT79L72 2 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC MARCH 2004 REGISTER MANUAL The XRT79L72 is a two channel, ATM UNI/PPP Physical Layer Processor with integrated DS3/E3 framing controllers and Line Interface Units with Jitter Attenuators that are designed to support ATM direct

dmo 265 r

Abstract: dmo 365 r MPC860 jtag AC16 GR-499-CORE I960 MPC860 XRT73L03 XRT74L73 XRT74L73IB
Contextual Info: XRT74L73 PRELIMINARY 3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER OCTOBER 2003 REV. P1.0.1 GENERAL DESCRIPTION The XRT74L73 3 Channel, ATM UNI/PPP Physical Layer Processor with integrated DS3/E3 framing controller is designed to support ATM direct mapping and

TR54016

Abstract: XRT86VL34 XRT86VL34IB E1 frame
Contextual Info: XRT86VL34 QUAD T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION APRIL 2011 REV. V1.2.1 GENERAL DESCRIPTION The XRT86VL34 is a four-channel 1.544 Mbit/s or 2.048 Mbit/s DS1/E1/J1 framer and LIU integrated solution featuring R3 technology Relayless, Reconfigurable, Redundancy .