0X000CFF Search Results

mbus

Abstract: SK 8022 ace dsc hen nu SM 8002 C
Contextual Info: IDT77V011 DATA PATH INTERFACE DPI TO UTOPIA LEVEL 2 TRANSLATION DEVICE Features ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ Single chip interface between multiple UTOPIA PHYs and a single Data Path Interface (DPI). Ideal for xDSL DSLAM and 25Mbps switching applications.

bfp760

Abstract: ADSP-TS201 reverse carry addition WPCT ADSP-21263 C-15 ts101 dsp application note boot kernel for the ADSP-21369 xr120xddddcccc "vector instructions" saturation
Contextual Info: ADSP-TS201 TigerSHARC Processor Programming Reference Revision 1.1, April 2005 Part Number 82-000810-01 Analog Devices, Inc. One Technology Way Norwood, Mass. 02062-9106 a Copyright Information 2005 Analog Devices, Inc., ALL RIGHTS RESERVED. This document may not be reproduced in any form without prior, express

77V011

Abstract: 77V400 IDT77011 IDT77V011 IDT77V400 IDTV400 intel 8008 cpu
Contextual Info: IDT77V011 Data Path Interface DPI to Utopia Level 2 Translation Device )HDWXU WXUHV ‹ Single chip interface between multiple UTOPIA PHYs and a single Data Path Interface (DPI). ‹ Ideal for xDSL DSLAM and 25Mbps switching applications. ‹ Supports ATM Forum UTOPIA Level 2 interface in both 8-bit

ADSP-TS201 SDRAM

Abstract: TigerSHARC DSP Instruction set specification ADSP-TS201
Contextual Info: TigerSHARC Embedded Processor ADSP-TS202S a KEY FEATURES 1149.1 IEEE-compliant JTAG test access port for on-chip emulation On-chip arbitration for glueless multiprocessing 500 MHz, 2.0 ns instruction cycle rate 12M bits of internal—on-chip—DRAM memory

smd w20

Abstract: adsp ts201 link port ts201 SMD transistor k23 y6 smd transistor 32X32 ADSP-TS202S
Contextual Info: TigerSHARC Embedded Processor ADSP-TS202S Preliminary Technical Data KEY FEATURES KEY BENEFITS 500 MHz, 2.0 ns Instruction Cycle Rate 12M Bits of Internal—On-Chip—DRAM Memory 25x25 mm 576-Ball Thermally Enhanced Ball Grid Array Package Dual Computation Blocks—Each Containing an ALU, a Multiplier, a Shifter, and a Register File

smd 03 jb3

Abstract: l3bc
Contextual Info: TigerSHARC Embedded Processor ADSP-TS202S a KEY FEATURES 1149.1 IEEE-compliant JTAG test access port for on-chip emulation On-chip arbitration for glueless multiprocessing 500 MHz, 2.0 ns instruction cycle rate 12M bits of internal—on-chip—DRAM memory

Fcc907

Abstract: F2MC-16
Contextual Info: CM42-00327-1E FUJITSU SEMICONDUCTOR CONTROLLER MANUAL 2 F MC-16 FAMILY 16-BIT MICROCONTROLLER EMBEDDED C PROGRAMMING MANUAL FOR fcc907 2 F MC-16 FAMILY 16-BIT MICROCONTROLLER EMBEDDED C PROGRAMMING MANUAL FOR fcc907 FUJITSU LIMITED PREFACE • Objectives and Intended Reader

Contextual Info: IDT77V011 Data Path Interface DPI to Utopia Level 2 Translation Device )HDWXU WXUHV ‹ Single chip interface between multiple UTOPIA PHYs and a single Data Path Interface (DPI). ‹ Ideal for xDSL DSLAM and 25Mbps switching applications. ‹ Supports ATM Forum UTOPIA Level 2 interface in both 8-bit

ADSP2191

Abstract: ADSP-2191 AN-572
Contextual Info: a AN-572 APPLICATION NOTE One Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106 • 781/329-4700 • World Wide Web Site: http://www.analog.com Overlay Linking on the ADSP-219x By David Starr OVERVIEW This applications note is for software designers starting

doorbell project

Abstract: VIA 1394 80C32 TSB43AA82 TSB43AA82A TSB42AA82 LynxSoft app abstract
Contextual Info: TSB43AA82 iSphynxII Lynxsoft SBPĆ2 Target Firmware Programmer's Guide User’s Guide June 2003 Catalog Interface Solutions SLLU061 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries TI reserve the right to make corrections, modifications,

ADSP-TS202S

Abstract: ADSP-TS202
Contextual Info: TigerSHARC Embedded Processor ADSP-TS202S a KEY FEATURES KEY BENEFITS 500 MHz, 2.0 ns instruction cycle rate 12M bits of internal—on-chip—DRAM memory 25 mm x 25 mm 576-ball thermally enhanced ball grid array package Dual-computation blocks—each containing an ALU, a multiplier, a shifter, and a register file

0251X

Abstract: ADSP-TS202S smd code AA5 ADSP-TS201 SDRAM ADSP-TS201
Contextual Info: TigerSHARC Embedded Processor ADSP-TS202S a KEY FEATURES 1149.1 IEEE-compliant JTAG test access port for on-chip emulation On-chip arbitration for glueless multiprocessing 500 MHz, 2.0 ns instruction cycle rate 12M bits of internal—on-chip—DRAM memory

32X32

Abstract: ADSP-TS202S ds206 l3bc ADDR31-0 b14 smd
Contextual Info: PRELIMINARY TECHNICAL DATA TigerSHARC Embedded Processor ADSP-TS202S a Preliminary Technical Data KEY FEATURES 500 MHz, 2.0 ns Instruction Cycle Rate 12M Bits of Internal—On-Chip—DRAM Memory 25؋25 mm 576-Ball Thermally Enhanced Ball Grid Array Package

Contextual Info: TigerSHARC Embedded Processor ADSP-TS202S a KEY FEATURES 1149.1 IEEE-compliant JTAG test access port for on-chip emulation On-chip arbitration for glueless multiprocessing 500 MHz, 2.0 ns instruction cycle rate 12M bits of internal—on-chip—DRAM memory