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    TE Connectivity

    TE Connectivity GA10K3A1012I

    NTC Thermistors DISC-10K @25C 0.1C FROM 0TO70C
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    TTI GA10K3A1012I Bulk 1 1
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    • 100 $5.08
    • 1000 $5.03
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    TE Connectivity GA100K6A1014-3

    NTC Thermistors DISC-100K@25+/-0.2C FROM 0TO70
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    TTI GA100K6A1014-3 Each 100
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    • 100 $4.71
    • 1000 $4.19
    • 10000 $4.07
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    TE Connectivity GA100K6A91

    NTC Thermistors DISC-100K@25+/-0.2C FROM 0TO70
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    TTI GA100K6A91 Each 100
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    TE Connectivity GA100K6A1014-2

    NTC Thermistors DISC-100K@25+/-0.2C FROM 0TO70
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    TTI GA100K6A1014-2 Each 5,000
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    • 10000 $3.74
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    TE Connectivity GA100K6A1014-1

    NTC Thermistors DISC-100K@25+/-0.2C FROM 0TO70
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    TTI GA100K6A1014-1 Each 100
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    0TO70 Datasheets Context Search

    Catalog Datasheet Type Document Tags PDF

    Contextual Info: TOSHIBA TC5164 5 805AJ/AFT/AJS/AFTS-40,-50 TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS 8,388,6O8-WORD X8-BIT EDO (HYPER PAGE) DYNAMIC RAM DESCRIPTION The TC5164(5)805AJ/AFT/AJS/AFTS is an EDO (hyper page) dynamic RAM organized as 8,388,608


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    tc5164805aj/aft/ajs/afts-40805aj/aft/ajs/afts32-pin PDF

    K7A323600M

    Abstract: K7B321825M-QC65 K7A321800M
    Contextual Info: K7A323600M K7A321800M 1Mx36 & 2Mx18 Synchronous SRAM Document Title 1Mx36 & 2Mx18-Bit Synchronous Pipelined Burst SRAM Revision History Rev. No. History Draft Date Remark 0.0 1. Initial draft May. 10. 2001 Advance 0.1 1. Add 165FBGA package Aug. 29. 2001 Preliminary


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    k7a323600mk7a321800m1mx362mx18+42mx18-bit165fbgak7a3236k7b321825m-qc65 PDF

    K7M321825M

    Abstract: K7M321825M-QC75 K7M323625M K7M323625M-QC75
    Contextual Info: K7M323625M K7M321825M 1Mx36 & 2Mx18 Flow-Through NtRAMTM Document Title 1Mx36 & 2Mx18-Bit Flow Through NtRAMTM Revision History Rev. No. History Draft Date Remark 0.0 1. Initial document. May. 10. 2001 Preliminary 0.1 1. Add 165FBGA package Aug. 29. 2001 Preliminary


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    k7m323625mk7m321825m1mx362mx18+52mx18-bit165fbgax18/x36k7m321825m-qc75k7m323625m-qc75 PDF

    K7N401801B

    Abstract: K7N403601B
    Contextual Info: K7N403601B K7N401801B 128Kx36 & 256Kx18 Pipelined NtRAMTM Document Title 128Kx36 & 256Kx18-Bit Pipelined NtRAMTM Revision History History Draft Date Remark 0.0 1. Initial document. May. 15. 2001 Preliminary 0.1 1. Changed DC parameters Icc ; from 350mA to 290mA at -16,


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    k7n403601bk7n401801b128kx36256kx18+5256kx18-bit350ma290ma330ma270ma PDF

    K7B801825B

    Abstract: K7B803625B
    Contextual Info: K7B803625B K7B801825B 256Kx36 & 512Kx18 Synchronous SRAM Document Title 256Kx36 & 512Kx18-Bit Synchronous Burst SRAM Revision History Rev. No. History Draft Date Remark 0.0 Initial draft May. 18 . 2001 Preliminary 0.1 Add x32 org part and industrial temperature part


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    k7b803625bk7b801825b256kx36512kx18+3512kx18-bit119bga225mhz PDF

    K7N161801A

    Abstract: K7N163601A
    Contextual Info: K7N163601A K7N161801A 512Kx36 & 1Mx18 Pipelined NtRAM TM Document Title 512Kx36 & 1Mx18-Bit Pipelined NtRAMTM Revision History Rev. No. History Draft Date Initial document. Add JTAG Scan Order Add x32 org and industrial temperature . Add 165FBGA package Speed bin merge.


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    k7n163601ak7n161801a512kx361mx18+31mx18-bit165fbgak7n1636 PDF

    DG381AAK

    Contextual Info: Tem ic DG381A/384A/387A/390A Semiconductors CMOS Analog Switches Features Benefits Applications • • • • • Full Rail-to-Rail Analog Signal Range • Minimizes Signal Error • Low Power Dissipation • Low Level Switching Circuits • Programmable Gain Amplifiers


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    dg381a/384a/387a/390adg180plus-40pendg381a+3s-52880--rev28-apr-97dg381aak PDF

    Contextual Info: SC11027 Parallel Bus Modem Controller 'V ' SIERRA SEMICONDUCTOR □ D irect interface to SC11016 single chip modem □ Complete "AT" command set in firmware □ □ □ □ Auto power down Built-in UART Direct IBM PC XT bus interface 28-pin DIP or PLCC package


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    sc1102728-pinsc11016 PDF

    Contextual Info: K7A163608A K7A163208A K7A161808A PRELIMINARY 512Kx36/x32 & 1Mx18 Synchronous SRAM Document Title 512Kx36/x32 & 1Mx18-Bit Synchronous Pipelined Burst SRAM Revision History Rev. No. 0.0 0.1 History Draft Date Remark 1. Initial draft 1. Add x32 org and industrial temperature


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    k7a163608ak7a163208ak7a161808a512kx36/x32+21mx181mx18-bit PDF

    LD111CJ

    Abstract: ld111 ld110 ld110 design a BCD counter using j-k flipflop 3 phase digital voltmeter circuit diagram LD111 LD-110 D1980 4512 PIN DIAGRAM COUNTER LED bcd
    Contextual Info: s 3 Vi digit A/D converter set designed fo r . . . S ilic o n ix BEN EFITS o Two V oltage Ranges <1.999 V 1 9 9 .9 m V w ith Single Resistor Change H ig h P e rfo rm a n c e D ig ita l V o ltm e te rs and i D ig ita l P a n e l M e te rs W ide Sampling Rate: 1 /3 to 12/Second


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    12/secondld111/114d1980ld111cj+8ld111 ld110ld110design a bcd counter using j-k flipflop3 phase digital voltmeter circuit diagramld111ld-1104512 pin diagramcounter led bcd PDF

    sab80188

    Abstract: SAB 8086 80188 siemens EM 235 cn
    Contextual Info: 47E » • SIEMENS B235b05 GG313b4 T « S I E G SIEMENS AKTIENGESELLSCHAF High-lntegration SAB 80188/80188-1 8-Bit Microprocessor Preliminary SAB 80188 8 MHz • Integrated feature set - enhanced SAB 8088-2 CPU - clock generator - 2 independent high-speed DMAchannels


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    b235b05gg313b416-bitt-49-17-07+7fl235bossab80188fi23sbdst-49-77-07sab 808680188siemens em 235 cn PDF

    Contextual Info: » « H Y U N D A I e r ie s 1M x 4H_bŸjt 5C1M40 S4 0D R3 ABM Sw ,th 4C A S PRELIMINARY DESCRIPTION The HY514403B is the new generation and fast dynamic RAM organized 1,048,576 x 4-bit. The HY514403B has four CASs CAS0-3 which control corresponding data I/O port in conjunction with OE(eg. CSSO controls DQO,


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    5c1m40hy514403b1ac15-00-may944b750fi6+2hy514403bjhy514403bu PDF

    Contextual Info: KM64B261A BiCMOS SRAM 65,536 WORD x 4 Bit High-Speed BiCMOS Static RAM FEATURES GENERAL DESCRIPTION • Fast Access Time: 6, 7, 8 ns max. • Low Power Dissipation Standby (TTL) : 90mA (max.) (CM O S): 20mA (max.) • Operating Current : 160mA (f = 100 MHz.)


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    km64b261a160ma28-soj-3qo144-bit+1200mv PDF

    JA723

    Abstract: 723C HA723CN "Precision Voltage Regulator" 0405B LA723CN MA723 0581B ha723 precision voltage regulator
    Contextual Info: Product specification Philip« Semiconductor« Linear Product* Precision voltage regulator |iA723/723C PIN CONFIGURATION DESCRIPTION The mA723/ iA 723C is a monolithic precision voltage regulator capable of operation in positive or negative supplies as a series,


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    ia723/723cua723ua723cja723+8723cha723cnprecision voltage regulator0405bla723cnma7230581bha723 PDF

    scr drive circuit diagram

    Abstract: SCR Gate Drive 3 phase scr drive circuit diagram 400 amp SCR used for welding rectifier scr gate driver ic 600 A SCR firing converter circuit SCR gate drive circuit 5600 uF 1600 V scr drive circuit scr driving
    Contextual Info: T e m ic SÌ9143 S e m i c o n d u c t o r s Current Sharing Controller for High Performance Processors Features • • • • • • Automatic True Current Sharing with Parallel Converters External SCR Drive for Fault Protection Over-Voltage Protection


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    s-5536203-nov-97si9143scr drive circuit diagram+9scr gate drive3 phase scr drive circuit diagram400 amp scr used for welding rectifierscr gate driver ic 600 ascr firing converter circuitscr gate drive circuit5600 uf 1600 vscr drive circuitscr driving PDF

    RS-464

    Abstract: Teltone M-982 circuit diagram of calling bell 22-PIN M-982 T354 Call Progress Tone generator
    Contextual Info: tC e l x c d n e call p r o g r e s s t o n e RECEIVERS & TRANSMITTERS M -982 Precise Call Progress Tone Delector The Teltone M-982 is an integrated circuit precise tone detector for special purpose use in automatic following of switched telephone calls. The circuit uses low-power CMOS


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    m-98222-pin0to70vss-22+622121-20thrs-464teltone m-982circuit diagram of calling bellt354call progress tone generator PDF

    ic tba 220

    Abstract: km6161002j KM6161002-17
    Contextual Info: SAMSUNG ELEC T R O N I C S INC b7E D • □ □ 1 7 b clö SID SriGK PRELIMINARY KM6161002 CMOS SRAM 65,536 WORD x 16 Bit High-Speed CMOS Static RAM FEATURES GENERAL DESCRIPTION • Fast Access Time: 15, 17, 20ns Max. • Low Power Dissipation Standby (TTL)


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    km6161002km6161002j-15230makm6161002j-17+8220makm6161002j-20210makm6161002j44-pinq0177dsic tba 220km6161002-17 PDF

    K7A161801M

    Abstract: K7A163601M advh
    Contextual Info: K7A163601M K7A161801M 512Kx36 & 1Mx18 Synchronous SRAM Document Title 512Kx36 & 1Mx18-Bit Synchronous Pipelined Burst SRAM Revision History Rev. No. History Draft Date Remark 0.0 Initial draft Jan. 18. 1999 Preliminary 0.1 1. Update ICC & ISB values. 2. Remove tCYC 117MHz -85


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    k7a163601mk7a161801m512kx361mx18+61mx18-bit117mhz150ma110ma130maadvh PDF

    TMP68301

    Abstract: 301-AK-2 TLCS-68000 TMP68301AKF-8 TMP68301AKFR-8 TMP68HC000 68HC000 TMP6830 TMP68301A TMP68301AK
    Contextual Info: TOSHIBA TMP68301AK Part 3. TMP68301AKF-8 TMP68301AKFR-8 1. Introduction The TMP68301AK uses the 68HC000, the CMOS version of the 68000, as its core processor. The TMP68301AK includes a serial interface, p arallel interface, tim er, and in te rru p t controller. The


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    tmp68301aktmp68301akf-8tmp68301akfr-868hc000+732-bittmp68301301-ak-2tlcs-68000tmp68hc000tmp6830tmp68301a PDF

    NC-2H

    Abstract: K7B161825A K7B163225A K7B163625A
    Contextual Info: K7B163625A K7B163225A K7B161825A Preliminary 512Kx36/32 & 1Mx18 Synchronous SRAM Document Title 512Kx36/x32 & 1Mx18-Bit Synchronous Burst SRAM Revision History Rev. No. 0.0 0.1 0.2 History 1. Initial draft 1. Add JTAG Scan Order 1. Add x32 org and industrial temperature .


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    k7b163625ak7b163225ak7b161825a512kx36/32+51mx18512kx36/x321mx18-bit165fbganc-2h PDF

    K7N161801A

    Abstract: K7N163201A K7N163601A
    Contextual Info: K7N163601A K7N163201A K7N161801A Preliminary 512Kx36/32 & 1Mx18 Pipelined NtRAMTM Document Title 512Kx36/32 & 1Mx18-Bit Pipelined NtRAMTM Revision History Rev. No. 0.0 0.1 0.2 0.3 Draft Date History 1. Initial document. 1. Add JTAG Scan Order 1. Add x32 org and industrial temperature .


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    k7n163601ak7n163201ak7n161801a512kx36/32+41mx181mx18-bit165fbgak7n1636 PDF

    K7A801801B

    Abstract: K7A803201B K7A803601B
    Contextual Info: K7A803601B K7A803201B K7A801801B PRELIMINARY 256Kx36 & 256Kx32 & 512Kx18 Synchronous SRAM Document Title 256Kx36 & 256Kx32 & 512Kx18-Bit Synchronous Pipelined Burst SRAM Revision History Rev. No. 0.0 0.1 0.2 History Draft Date Remark Initial draft 1. Delete pass- through


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    k7a803601bk7a803201bk7a801801b256kx36+3256kx32512kx18512kx18-bit PDF

    K7A161801A

    Abstract: K7A163201A K7A163601A
    Contextual Info: K7A163601A K7A163201A K7A161801A PRELIMINARY 512Kx36/32 & 1Mx18 Synchronous SRAM Document Title 512Kx36/32 & 1Mx18-Bit Synchronous Pipelined Burst SRAM Revision History Rev. No. 0.0 0.1 0.2 History Draft Date Remark 1. Initial draft 1. Add x32 org and industrial temperature .


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    k7a163601ak7a163201ak7a161801a512kx36/32+31mx181mx18-bitk7a1636 PDF

    Contextual Info: bq4013/bq4013Y BENCHMARQ 128Kx8 Nonvolatile SRAM Features General Description > Data retention in the absence of power The CMOS bq4013 is a nonvolatile 1,048,576-bit static RAM organized as 131,072 words by 8 bits. The in teg ral control circuitry and lithium energy source provide reli­


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    bq4013/bq4013y128kx8bq4013576-bit+232-pin10-year PDF