0DDD72 Search Results

Z301-10

Abstract: D58ZOV271RA09 D58ZO VARISTOR 58819 z950 Z350-01 z301 150vac Z151-02 Z271-09 z30001
Contextual Info: 5 8 E s a X i m u m Part Number 5m m D isc D iam eter D58ZOV110R AOO D58ZOV140R A00 Actual Part Marking Continuous Rated Voitape AC RMS DC Volts Volts R I R a t i n n s E Ie ct r i c a I Rated Sinale Pulse Transient E nergy Peak 2ms 10/1000|js 8/20fiS Joules

V96SSC25LP

Contextual Info: ‘ÌOOMEOO 0 0 0 0 3 0 3 ISA V96SSC • * * ▼ / Rev. BO HIGH-INTEGRATION SYSTEM CONTROLLER FOR ¡960 Sx/Jx AND PowerPC 401 Gx PROCESSORS • Direct interface to ¡960Sx/Jx and PPC401Gx processors • High-performance burst DRAM controller • Two-channel fly-by DMA controller

Contextual Info: FX803 Audio Signalling Processor SIGNAL INPUT 8IAS Fig. 1 FX803 Audio Signalling Processor F X 80 3 Audio Signalling Processor As part of the DBS 800 System, this audio signalling processor will provide an inband tone signalling facility tor PMR radio systems. Signalling systems supported include

Contextual Info: ^004200 □□□□102 MST • V961PBC •" V Rev. B1 LOCAL BUS TO PCI BRIDGE FOR i960 Jx AND PowerPC 401 Gx PROCESSORS " • Glueless interface between ¡960Jx, PPC401 Gx processors and the PCI bus • Large, 576-byte FIFOs using V3's unique D y n a m ic B a n d w id t h A l l o c a t i o n ™ architecture

Contextual Info: P a r a e ï g PDM44028 m 64K x 18 Fast CMOS Synchronous Static SRAM with Interleaved Burst Counter Features Description U Interfaces directly with the i486 , Pentium™ processors 80, 66, 60, 50,40 MHz □ High Speed Access Times - Clock to data valid times:

Contextual Info: •iOONSna 0 0 0 0 0 4 7 V960PBC V 313 Rev. B1 LOCAL BUS TO PCI BRIDGE FOR i960 Sx PROCESSORS “ • Glueless interface between ¡960Sx processors and the PCI bus • Large, 576-byte FIFOs using V3’s unique D y n a m ic B a n d w id t h A l l o c a t i o n architecture

Contextual Info: • S00M200 V96BMC jj ; v D000M54 STO Rev. D HIGH PERFORMANCE BURST DRAM CONTROLLER - FOR i960Cx/Hx/Jx PROCESSORS • Pin/Software compatible with earlier V96BMC. • Integrated Page Cache Management. • Direct interfaces to i960Cx/Hx/Jx processors. • 2Kbyte burst transaction support.

Contextual Info: TG04200 if QQQD117 V 9 6 2 P B C SÔQ Rev. B1 LOCAL BUS TO PCI BRIDGE FOR i960 Cx/Hx PROCESSORS » Ic0* v • Glueless interface between i960Cx/Hx processors and the PCI bus • 2 channel DMA controller • Bi-directional mailboxes w/doorbell interrupts • Large, 576-byte FIFOs using V3’s unique