08AUG2002 Search Results

Contextual Info: 100355 Low Power Quad Multiplexer/Latch General Description The 100355 contains four transparent latches, each of which can accept and store data from two sources. When both Enable En inputs are LOW, the data that appears at an output is controlled by the Select (Sn) inputs, as shown in the Operating Mode table. In addition to routing data from either D0 or

27014QS

Abstract: 5962R9059001SZA
Contextual Info: 54AC05 Hex Inverter with Open Drain Outputs General Description Features The ’AC05 contains six inverters. n Outputs sink 24 mA n Open drain for wired NOR function n Standard Microcircuit Drawing SMD 5962-9059001 Logic Symbol IEEE/IEC DS100981-1 Connection Diagrams

marking ACQ

Abstract: ACQ374 ACTQ374
Contextual Info: 54ACQ374 • 54ACTQ374 Quiet Series Octal D Flip-Flop with TRI-STATE Outputs General Description The ’ACQ/’ACTQ374 is a high-speed, low-power octal D-type flip-flop featuring separate D-type inputs for each flip-flop and TRI-STATE outputs for bus-oriented applications. A buffered Clock CP and Output Enable (OE) are

Contextual Info: 100341 Low Power 8-Bit Shift Register General Description Features The 100341 contains eight edge-triggered, D-type flip-flops with individual inputs Pn and outputs (Qn) for parallel operation, and with serial inputs (Dn) and steering logic for bidirectional shifting. The flip-flops accept input data a setup

Contextual Info: SCAN921025 and SCAN921226 30-80 MHz 10 Bit Bus LVDS Serializer and Deserializer with IEEE 1149.1 JTAG and at-speed BIST General Description The SCAN921025 transforms a 10-bit wide parallel LVCMOS/LVTTL data bus into a single high speed Bus LVDS serial data stream with embedded clock. The

ACTQ16245

Contextual Info: 54ACTQ16245 16-Bit Transceiver with TRI-STATE Outputs General Description Features The ’ACTQ16245 contains sixteen non-inverting bidirectional buffers with TRI-STATE outputs and is intended for bus oriented applications. The device is byte controlled.

GA20 Application Form

Abstract: F9321 f9301
Contextual Info: May 2001 Rev. 1.03 PC87591E and PC87591S LPC Mobile Embedded Controller General Description Like members of National’s SuperI/O family, the PC87591x is PC01 and ACPI compliant. The National Semiconductor PC87591E and PC87591S are highly integrated, embedded controllers with an embedded-RISC core and integrated, advanced functions. Targeted for a wide range of portable applications that use the Low

marking A19

Abstract: UA 324 PC A27A Marking A19 sot23
Contextual Info: LPV321 Single/LPV358 Dual/LPV324 Quad General Purpose, Low Voltage, Low Power, Rail-to-Rail Output Operational Amplifiers General Description Features The LPV321/358/324 are low power 9µA per channel at 5.0V versions of the LMV321/358/324 op amps. This is

Contextual Info: 100325 Low Power Hex ECL-to-TTL Translator General Description Features The 100325 is a hex translator for converting F100K logic levels to TTL logic levels. Differential inputs allow each circuit to be used as an inverting, non-inverting or differential receiver. An internal reference voltage generator provides VBB

ACTQ04

Abstract: 54ACTQ04FMQB
Contextual Info: 54ACTQ04 Quiet Series Hex Inverter General Description The ’ACTQ04 contains six inverters and utilizes NSC Quiet Series technology to guarantee quiet output switching and improved dynamic threshold performance. FACT Quiet Series features GTO™ output control and undershoot corrector in addition to a split ground bus for superior ACMOS performance.

54ACT257FMQB

Contextual Info: 54AC257 • 54ACT257 Quad 2-Input Multiplexer with TRI-STATE Outputs General Description Features The ’AC/’ACT257 is a quad 2-input multiplexer with TRI-STATE outputs. Four bits of data from two sources can be selected using a Common Data Select input. The four

Contextual Info: 100351 Low Power Hex D Flip-Flop General Description Features The 100351 contains six D-type edge-triggered, master/ slave flip-flops with true and complement outputs, a pair of common Clock inputs CPa and CPb and common Master Reset (MR) input. Data enters a master when both CPa and

5962R9218601

Abstract: MV54ACTQ244-X MV54ACTQ244 ACQ24
Contextual Info: 54ACQ244 • 54ACTQ244 Quiet Series Octal Buffer/Line Driver with TRI-STATE Outputs General Description The ’ACQ/’ACTQ244 is an octal buffer and line driver designed to be employed as a memory address driver, clock driver and bus oriented transmitter or receiver which provides improved PC board density. The ACQ/ACTQ utilizes

Contextual Info: SCANSTA111 Enhanced SCAN bridge Multidrop Addressable IEEE 1149.1 JTAG Port General Description The SCANSTA111 extends the IEEE Std. 1149.1 test bus into a multidrop test bus environment. The advantage of a multidrop approach over a single serial scan chain is improved test throughput and the ability to remove a board

ecl 100131

Contextual Info: 100331 Low Power Triple D Flip-Flop General Description Features The 100331 contains three D-type, edge-triggered master/ slave flip-flops with true and complement outputs, a Common Clock CPC , and Master Set (MS) and Master Reset (MR) inputs. Each flip-flop has individual Clock (CPn), Direct

RM54ACT138

Abstract: RM54ACT138sfa DIODE smd marking E3
Contextual Info: 54AC138 • 54ACT138 1-of-8 Decoder/Demultiplexer General Description Features The ’AC/’ACT138 is a high-speed 1-of-8 decoder/ demultiplexer. This device is ideally suited for high-speed bipolar memory chip select address decoding. The multiple input enables allow parallel expansion to a 1-of-24 decoder

UL2002

Contextual Info: TH I S DRAW I NG IS UNPUBLI S HE D. C O P Y RI G HT 20 RELEASED BY TYCO ELECTRONICS CORPORATION. F OR ALL PUBLICATION R 1G H T S 20 L OC FT RESERVED. REV I S IONS D I ST LTR DESCRIPTION DATE R E L E A S E D EC 0 G 3 B - 0 2 9 8 - 0 2 R E V I S E D EC 0 G 3 B - 0 3 4 0 - 0 2