A27A Search Results

TC514100

Abstract: 514100A
Contextual Info: 4,194,304 WORD X 1 BIT DYNAMIC RAM DESCRIPTION THE TC514100A is the new generation dynamic RAM organized 4,194,304 word by 1 bit. The TC514410ASJ/AZ/AFT utilizes Toshiba’s CMOS silicon gate process technology as well as advanced circuit

LPV321M5

Abstract: LPV321 LPV324 LPV358 SC70-5
Contextual Info: LPV321 Single/LPV358 Dual/LPV324 Quad General Purpose, Low Voltage, Low Power, Rail-to-Rail Output Operational Amplifiers General Description Features The LPV321/358/324 are low power 9µA per channel at 5.0V versions of the LMV321/358/324 op amps. This is

2561b

Abstract: CPU 314 IFM 8kx1 RAM cy17 ALI chipset fast page mode dram controller CY2254ASC-2 CY27C010 CY82C691 CY82C693
Contextual Info: PRELIM INARY CY82C691 Pentium hyperCache™ Chipset System Controller Features Supports mixed standard page-mode and EDO DRAMs Supports the VESA Unified Memory Architecture VUMA Support for standard 72-bit-wide DRAM banks Supports non-symmetrical DRAM banks

sf 127d

Abstract: 127D IC51-1324-828 SN74ABT3611 D103E
Contextual Info: SN74ABT3611 64 x 36 CLOCKED FIRST-IN, FIRST-OUT MEMORY SCBS127D - JULY 1992 - REVISED SEPTEMBER 1995 Free-Running CLKA and CLKB Can Be Asynchronous or Coincident 64 x 36 Clocked FIFO Buffering Data From Port A to Port B Mailbox-Bypass Register In Each Direction

Contextual Info: CMOS Clocked FIFO With Bus Matching and Byte Swapping IDT723613 64x36 Integrated Device Technology, Inc. FEATURES: • Free-running CLKA and CLKB may be asynchronous or coincident permits simultaneous reading and writing of data on a single clock edge • 64 x 36 storage capacity FIFO buffering data from Port A

Contextual Info: CMOS SyncFIFO IDT723611 64x36 Integrated Device Technology, Inc. FEATURES: • Free-running CLKA and CLKB may be asynchronous or coincident permits simultaneous reading and writing of data on a single clock edge • 64 x 36 storage capacity • Synchronous data buffering from Port A to Port B

Contextual Info: In te g ra te d D e v i e T e d h n o Jo g y , lie . CMOS Triple Bus SyncFlFO1 With Bus-Matching 256 x 36 x 2, 512 x 36 x 2, 1024x36x2 PRELIMINARY IDT723626 IDT723636 IDT723646 NOTE: There are two errata notices at the end of this data sheet. The May 20 errata describes corrections that have

Contextual Info: CMOS SyncBiFlFO WITH BUS MATCHING AND BYTE SWAPPING 64 x 36 x 2 IDT723614 Integrated Device Technology, Inc. FEATURES: • Free-running CLKA and CLKB can be asynchronous or coincident simultaneous reading and writing of data on a single clock edge is permitted

Contextual Info: 3.3 VOLT CMOS CLOCKED FIFO WITH BUS-MATCHING AND BYTE SWAPPING 64 x 36 • Passive parity checking on each Port • Parity Generation can be selected for each Port • Available in 132-pin plastic quad flat package PQF , or space saving 120-pin thin quad flat package (TQFP)

uPD765

Abstract: DP8473 N82077 NEC765A PC01 PC87413 PC87414 PC87416 PC87417 tag 9320
Contextual Info: November 2001 Rev 1.1 PC87413, PC87414, PC87416, PC87417 LPC ServerI/O for Servers and Workstations General Description The National Semiconductor PC8741x family of LPC ServerI/O devices “PC8741x” comprises highly integrated Advanced I/O products. The PC8741x is targeted for a wide

IC51-1324-828

Abstract: IDT723612
Contextual Info: IDT723612 CMOS SyncBiFIFO 64 x 36 x 2 Integrated Device Technology, Inc. • • • • Low-power advanced CMOS technology Supports clock frequencies up to 67 MHz Fast access times of 10ns Available in 132-pin plastic quad flat package PQF or space-saving 120-pin thin quad flat package (TQFP)

IDT723611

Abstract: IDT72V3611
Contextual Info: IDT72V3611 3.3 VOLT CMOS SyncFIFO 64 x 36 COMMERCIAL TEMPERATURE RANGE 3.3 VOLT CMOS SyncFIFO 64 x 36 PRELIMINARY IDT72V3611 Integrated Device Technology, Inc. • Parity Generation can be selected for each Port • Available in 132-pin Plastic Quad Flatpack PQF or

IDT72V3626

Abstract: IDT72V3636 IDT72V3646
Contextual Info: 3.3 VOLT CMOS TRIPLE BUS SyncFIFOTM WITH BUS-MATCHING 256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2 FEATURES: PRELIMINARY IDT72V3626 IDT72V3636 IDT72V3646 • Serial or parallel programming of partial flags • Big- or Little-Endian format for word and byte bus sizes

IC51-1324-828

Abstract: IDT723612 IDT72V3612 B18-B26
Contextual Info: 3.3 VOLT CMOS SyncBiFIFOTM 64 x 36 x 2 FEATURES: ♦ ♦ ♦ ♦ Two independent clocked FIFOs 64 x 36 storage capacity each buffering data in opposite directions ♦ Supports clock frequencies up to 83 MHz ♦ Fast access times of 8ns ♦ Free-running CLKA and CLKB can be asynchronous or

IC51-1324-828

Abstract: IDT723613 IDT72V3613
Contextual Info: IDT72V3613 3.3 VOLT CMOS CLOCKED FIFO WITH BUS-MATCHING AND BYTE SWAPPING 64 x 36 FEATURES: ♦ ♦ ♦ Passive parity checking on each Port Parity Generation can be selected for each Port Available in 132-pin plastic quad flat package PQF , or space saving 120-pin thin quad flat package (TQFP)

Contextual Info: IDT72V3613 3.3 VOLT CMOS CLOCKED FIFO WITH BUS-MATCHING AND BYTE SWAPPING 64 x 36 • • FEATURES: • • • • • • • • • • • • • 64 x 36 storage capacity FIFO buffering data from Port A to Port B Supports clock frequencies up to 83MHz

Contextual Info: CMOS TRIPLE BUS SyncFIFOTM WITH BUS-MATCHING 256 x 36 x 2, 512 x 36 x 2 1,024 x 36 x 2 FEATURES: • • • • • • • • • Memory storage capacity: IDT723626 – 256 x 36 x 2 IDT723636 – 512 x 36 x 2 IDT723646 – 1,024 x 36 x 2 Clock frequencies up to 83 MHz 8ns access time

BV 3145

Contextual Info: CMOS Clocked FIFO With Bus Matching and Byte Swapping 64 x 36 FE ATURES: • Free-running CLKA and CLKB may be asynchronous or coincident perm its sim ultaneous reading and w riting ot data on a single clock edge • 64 x 36 storage capacity FIFO buttering data trom Port A

Contextual Info: Integrated Devile Technology, lie. CMOS TRIPLE BUS SyncFIFOT WITH BUS-MATCHING AND BYTE SWAPPING 64 x 36 x 2 FEATURES: • Two independent FIFOs 64 X 36 storage capacity each buffer data between bidirectional 36-bit port A and two unidirectional 18/9-bit ports (Port B transmits, Port C

cmc tpm 16

Contextual Info: CMOS Clocked FIFO With Bus Matching and Byte Swapping Integrated Device Technology, Inc. IDT723613 6 4 x 3 6 FEATURES: • Free-running C LKA and CLKB may be asynchronous or coincident perm its sim ultaneous reading and w riting of data on a single clock edge

IC51-1324-828

Abstract: IDT723612 IDT72V3612
Contextual Info: 3.3 VOLT CMOS SyncBiFIFOTM 64 x 36 x 2 FEATURES: ♦ ♦ ♦ ♦ Two independent clocked FIFOs 64 x 36 storage capacity each buffering data in opposite directions ♦ Supports clock frequencies up to 83 MHz ♦ Fast access times of 8ns ♦ Free-running CLKA and CLKB can be asynchronous or

7170

Contextual Info: ICM7170 jaP-Compatible Real-Time Clock GENERAL DESCRIPTION FEATURES The ICM7170 real time clock is a microprocessor bus compatible peripheral, fabricated using Harris’ silicon gate CMOS LSI process. An 8 -bit bidirectional bus is used for the data I/O circuitry. The clock is set or read by accessing the

PowerPC 603 RISC Microprocessor Users Manual

Contextual Info: MPE603E/D Motorola Order Number 9/97 REV. 0.1 PowerPC Advance Information EC603e Embedded RISC Microprocessor Technical Summary This document provides an overview of the EC603e microprocessor features, including a block diagram showing the major functional components. It also provides an overview of

S64B

Contextual Info: Order this document by MPC603/D 12/93 REV 1 Advance Information PowerPC 603ra RISC Microprocessor Technical Summary This document provides an overview of the MPC603 features, including a block diagram showing the major functional components. It also provides an overview of the PowerPC