01AUG09 Search Results

XR20V2172IL64

Abstract: XR20V2172IL64-F
Contextual Info: XR20V2172 TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER JULY 2008 REV. 1.0.1 GENERAL DESCRIPTION FEATURES The XR20V21721 V2172 is a high performance two channel universal asynchronous receiver and transmitter (UART) with 64 byte TX and RX FIFOs, a

Contextual Info: XRT8001 WAN Clock for T1 and E1 Systems October 2001-1 GENERAL DESCRIPTION • Generates Output Clock Frequencies Ranging The XRT8001 WAN Clock is a dual-phase-locked loop chip that generates two very low jitter output clock signals that can be used for synchronization clocks in

Contextual Info: XRT73L02M xr TWO CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT MAY 2003 GENERAL DESCRIPTION The XRT73L02M is a two-channel fully integrated Line Interface Unit LIU for E3/DS3/STS-1 applications. It incorporates independent Receivers, Transmitters in a single 100 pin TQFP package.

30186

Contextual Info: XRT8010 312MHZ CLOCK & CRYSTAL MULTIPLIER WITH LVDS OUTPUTS NOVEMBER 2003 REV. 1.0.2 DESCRIPTION • FEATURES The XRT8010 is a monolithic analog phase locked loop that provides a high frequency LVDS clock output, using a low frequency crystal or reference

Contextual Info: XR19L202 TWO CHANNEL INTEGRATED UART AND RS-232 TRANSCEIVER JULY 2007 REV. 1.0.1 GENERAL DESCRIPTION APPLICATIONS The XR19L202 L202 is a highly integrated device that combines a full-featured two channel Universal Asynchronous Receiver and Transmitter (UART) and RS232 transceivers. The L202 is designed to operate with a

N0044

Abstract: divide by 60 XRS10L240
Contextual Info: EXSTOR XRS10L140 SERIAL ATA II: PORT MULTIPLIER JANUARY 2009 REV. 1.05 test and loopback features is achieved in a low cost and lower power implementation. FEATURES GENERAL FEATURES • Five independent 3/1.5Gbps SATA ports. • Connects 1 host port to 4 device ports.

RS-232 IBIS models

Abstract: 64-QFN XR19L222IL64F XR19L222IL64
Contextual Info: XR19L222 TWO CHANNEL INTEGRATED UART AND RS-232 TRANSCEIVER JULY 2007 REV. 1.0.1 GENERAL DESCRIPTION APPLICATIONS The XR19L222 L222 is a highly integrated device that combines a full-featured two channel Universal Asynchronous Receiver and Transmitter (UART) and RS232 transceivers. The L222 is designed to operate with a

relay finder t29

Abstract: T74 relay finder t29 PLL 2400 MHZ
Contextual Info: XRT8000 -WAN Clock Synchronizer/Adapter for Communications HomeNewsCareers Investor Relations Contact Us PartnerNet Login Search CommunicationsInterfacePower Management XRT8000 Support Info Request How to Order Samples How to Buy Print this page WAN Clock Synchronizer/Adapter for Communications

Contextual Info: XRT59L91 Single-Chip E1 Line Interface Unit October 1999-1 FEATURES l Complete E1 CEPT line interface unit (Transmitter and Receiver) l Supports both Local- and Remote-Loop back Operations l Generates transmit output pulses that are compliant with the ITU-T G.703 Pulse Template

Contextual Info: XR16V794 -High Performance 2.25V to 3.6V Quad UART with Fractional Baud Rate HomeNewsCareers Investor Relations Contact Us PartnerNet Login Search CommunicationsInterfacePower Management XR16V794 Support Info Request Print this page High Performance 2.25V to 3.6V Quad UART with Fractional

MDIO communication protocol

Abstract: ibis sata MDC 1200 N0021 XRS10L120
Contextual Info: EXSTOR XRS10L120 SERIAL ATA II: PORT MULTIPLIER JUNE 2009 REV. 1.06 test and loopback features is achieved in a low cost and lower power implementation. FEATURES GENERAL FEATURES • Three independent 3/1.5Gbps SATA ports. • Connects 1 host port to 2 device ports.

Contextual Info: áç XRT71D00 E3/DS3/STS-1 JITTER ATTENUATOR SEPTEMBER 2001 REV. 1.2.0 GENERAL DESCRIPTION The XRT71D00 is a single channel, single chip Jitter Attenuator, that meets the Jitter transfer characteristic requirements specified in the ETSI TBR-24, Bellcore GR-499-CORE and GR-253-CORE standards.

2 pin ir receiver

Contextual Info: XR19L212 TWO CHANNEL INTEGRATED UART AND RS-232 TRANSCEIVER JULY 2007 REV. 1.0.1 GENERAL DESCRIPTION APPLICATIONS • Battery-Powered Equipment • Handheld and Mobile Devices • Handheld Terminals • Industrial Peripheral Interfaces • Point-of-Sale POS Systems

14411 baud rate generator

Abstract: XR16L2750
Contextual Info: XR16V2750 HIGH PERFORMANCE DUART WITH 64-BYTE FIFO SEPTEMBER 2007 REV. 1.0.3 GENERAL DESCRIPTION The XR16V27501 V2750 is a high performance dual universal asynchronous receiver and transmitter (UART) with 64 byte TX and RX FIFOs. The device operates from 2.25 to 3.6 volts with 5 Volt tolerant

Digital TV transmitter receivers block diagram

Contextual Info: XR-T5793 .the analog plus Quad E1 Line Interface Unit company TM June 1997-3 D Individual Channel Loss of Signal Detection, Local and Remote Digital Loopback FEATURES D Meets CCITT G.703 Pulse Mask Template for 2.048Mbps E1 Rates D Low Power, CMOS Technology

Ox086

Abstract: 552 93c46
Contextual Info: XR17V254 66MHZ PCI BUS QUAD UART WITH POWER MANAGEMENT SUPPORT JULY 2008 REV. 1.0.1 GENERAL DESCRIPTION The XR17V2541 V254 is a single chip 4-channel 66MHz PCI (Peripheral Component Interconnect) UART (Universal Asynchronous Receiver and Transmitter) solution,

Contextual Info: XR-T3588/89 .the analog plus V.35 Interface Receiver/Transmitter company TM June 1997-3 FEATURES APPLICATIONS D Compatible with ITU-T V.35 and Bell 306 Interface Requirements D High Speed Data Transmission Systems D TTL Input Compatibility D Short Haul Modems

Relay NAIS Ds

Abstract: E3252 SG 2368 ATA 2388 ic 393 NAIS tf relay tes 5-2422
Contextual Info: áç XRT72L50 SINGLE CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER OCTOBER 2003 REV. 1.2.1 GENERAL DESCRIPTION The XRT72L50, single Channel DS3/E3 Framer IC is designed to accept user data from the Terminal Equipment and insert this data into the payload bitfields within an outbound DS3/E3 Data Stream. Further, the Framer IC is also designed to receive an inbound DS3/E3 Data Stream from the Remote Terminal Equipment and extract out the user data.

24444

Abstract: XRT5683AID-F XRT5683AIDf XRT5683AID
Contextual Info: XR-T5683A .the analog plus PCM Line Interface Chip company TM June 1997-3 FEATURES D TTL Compatible Interface D Single 5V Supply D Device Can Be Used as a Line Interface Unit Without Clock Recovery D Receiver Input Can Be Either Balanced or Unbalanced APPLICATIONS

relay finder t29

Contextual Info: áç XRT71D03 3 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR SEPTEMBER 2001 REV. 1.2.0 GENERAL DESCRIPTION The XRT71D03 is a three channel, single chip Jitter Attenuator, that meets the Jitter transfer characteristics requirements specified in the ETSI TBR-24, Bellcore GR-499 and GR-253 standards.

AM 770 DENSITY TRANSMITTER

Abstract: wandel goltermann RFZ wandel goltermann sna-2
Contextual Info: XRT5894 Four-Channel E1 Line Interface 3.3V or 5.0V March 2000-3 FEATURES D Compliant with ITU G.703 Pulse Mask Template for 2.048Mbps (E1) Rates D Four Independent CEPT Transceivers D Logical Inputs Accept either 3.3V or 5.0V Levels D Ultra-Low Power Dissipation

SC16C752B

Contextual Info: XR16M752/XR68M752 HIGH PERFORMANCE DUART WITH 64-BYTE FIFO JUNE 2009 REV. 1.1.1 GENERAL DESCRIPTION The XR16M752/XR68M7521 M752 is a high performance dual universal asynchronous receiver and transmitter (UART) with 64 byte TX and RX FIFOs. The M752 operates from 1.62 to 3.63 volts. It

M1172

Abstract: 1152 si dlm QFN32 pad xr20m1172il32-f
Contextual Info: XR20M1172 TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO JUNE 2009 REV. 1.0.1 GENERAL DESCRIPTION FEATURES The XR20M11721 M1172 is a high performance two channel universal asynchronous receiver and transmitter (UART) with 64 byte TX and RX FIFOs and a selectable I2C/SPI slave interface. The M1172

XRT5997IV-F

Contextual Info: XRT5997 Seven-Channel E1 Line Interface Unit November 1999-2 FEATURES The Main features are as follows: l Consists of Seven 7 Independent E1 (CEPT) Line Interface Units (Transmitter and Receiver) l Generates Transmit Output Pulses that are Compliant with the ITU-T G.703 Pulse Template