0041A Search Results

LH77790A

Abstract: 16c40 LH77790 s9897 Pixel Magic 35
Contextual Info: ARM Evaluation Board KPI-0041A User Guide ARM DUI 0091A Open Access ARM Evaluation Board User Guide Change log Date Issue Change August 1998 A First release Proprietary notice ARM, EmbeddedICE, and Muliti-ICE are trademarks of ARM Limited. All other products or services mentioned herein may be trademarks of their respective owners.

Contextual Info: ispLSI 3256 High Density Programmable Logic Functional Block Diagram A1 OR Array A2 A3 B1 B2 B3 N C0 C1 C2 R D Q F1 Twin GLB F0 D Q E3 D Q E2 D Q E1 Global Routing Pool E0 C3 Output Routing Pool • 100% IEEE 1149.1 BOUNDARY SCAN COMPATIBLE F2 D Q Array

2057AE

Abstract: LTP2057AG 2757aa 2057 LED dot matrix display 5x7 LTP-2057AHR 2057A 2157 ae 2057 dot matrix LTP2757AA LTPG
Contextual Info: i iLITE-O N INC 31E D SS3b3fci7 G Q O SSn b ILTN ; u»j I IL-J u-J LxJ ùj L_i lJ L i I rrip 2057A/2157A QiT’TiTTrQ L1C 2657AA/2757AÄ 2.0" 5 x 7 SINGLE COLOR & MULTICOLOR DOT M A TR IX DISPLAYS FEATURES • • • • • • • • 2.0" INCH 50.8 mm M ATRIX HEIGHT.

PLSI 1016-60LJ

Abstract: PAL 007 pioneer pal16r8 programming algorithm PAL 008 pioneer lattice 1016-60LJ ISP Engineering Kit - Model 100 PLSI-2064-80LJ GAL16v8 programmer schematic GAL programming Guide ispLSI 2064-80LT
Contextual Info: Lattice Semiconductor Data Book 1996 Click on one of the following choices: • Table of Contents • Data Book Updates & New Products • Go to Main Menu 1996 Lattice Semiconductor Corporation. All rights reserved. ispLSI and pLSI Product Index Pins Density

isp1032

Abstract: lattice 1032-60LJ 1032E-8
Contextual Info: Specifications ispLSI and pLSI 1032 ispLSI and pLSI 1032 ® High-Density Programmable Logic Features Functional Block Diagram • HIGH-DENSITY PROGRAMMABLE LOGIC — High Speed Global Interconnect — 6000 PLD Gates — 64 I/O Pins, Eight Dedicated Inputs

tsop 3021

Contextual Info: ISSI IS 4 1 C 1 6 2 5 7 256K x 16 4-MBIT DYNAMIC RAM WITH FAST PAGE MODE JU LY 1998 FEATURES DESCRIPTION • Fast access and cycle time The IS S I IS41C16257 is a 262,144 x 16-bit highperformance CMOS Dynamic Random Access Memory. Fast Page Mode allows 512 random accesses within a

ten 5-2415

Abstract: LTA-1000P LTA-1000R
Contextual Info: riL IT E -O N r.- 31E D I NC I ITm í L T A -IO O O SS3b3b7 DOGSSSS 1 « L T N i S E R IE S BAR GRAPH ARRAY FEATURES • LARG E SEGMENTS, CLO SELY SPACED. • CHOICE OF S IX B R IG H T C O LO R S-R ED /B R IG H T RED / GREEN / YE LLO W / O RANG E / HIG H E F F I­

1048C

Abstract: cpga 476 1048C50LQI 1048C-70
Contextual Info: Specifications ispLSI and pLSI 1048C ® ispLSI and pLSI 1048C High-Density Programmable Logic Functional Block Diagram • HIGH-DENSITY PROGRAMMABLE LOGIC — 8000 PLD Gates — 96 I/O Pins, 12 Dedicated Inputs, 2 Global Output Enables — 288 Registers

1048C

Contextual Info: Specifications ispLSI and pLSI 1048C ispLSI and pLSI 1048C ® High-Density Programmable Logic Functional Block Diagram Output Routing Pool Output Routing Pool F7 F6 F5 F4 F3 F2 F1 F0 E7 E6 E5 E4 E3 E2 E1 E0 D7 A2 A4 IG N D Q Logic Global Routing Pool GRP

Contextual Info: Lattice' | Semiconductor I Corporation ispLSI9 and pLSt 1048C High-Density Programmable Logic Features Functional Block Diagram HIGH-DENSITY PROGRAMMABLE LOGIC — 8000 PLD Gates — 96 I/O Pins, 12 Dedicated Inputs, 2 Global Output Enables — 288 Registers

isp1032

Abstract: g10 smd transistor 5962-9308501MXC
Contextual Info: ispLSI 1032/883 In-System Programmable High Density PLD Features Functional Block Diagram • HIGH-DENSITY PROGRAMMABLE LOGIC — High Speed Global Interconnect — 6000 PLD Gates — 64 I/O Pins, Eight Dedicated Inputs — 192 Registers — Wide Input Gating for Fast Counters, State

led 7 segment anode 5101

Abstract: Q002 432PC y413 lto432xc
Contextual Info: ] f ." E C ]3 482SC SE R IE S .] ! T 1 0.4" D U A L D IG IT N U M ER IC D IS P L A Y S |LITE-0N INC 31E D 553b3b? 0002400 3 . -•'t ILTN FEA TU RES • 0.4 INCH 10.21 mm D IGIT HEIGHT. • CONTINUOUS UNIFORM SEGMENTS. • CHOICE OF FOUR BRIGHT C O L O R S -R E D /

LTC5836G

Abstract: LTC-5836E LTC5836R LTC5836E LTC-5836P DP 804 C LTC5836P LTC-5836 LTC-5000
Contextual Info: L ü L iü ü u iL jL jü SS3b3h7 00 0 2 4 3 ^ 6 31E D • ¡LITE-ON INC LIT LTC"5336 SERIES ILTN Œ G • .• " :Y . ï s z z p. •: Y -I-'. ■»•••• S X'.ù r ." C Y : :'V . ; :j - r ^ u - ia FEATURES • 0 .5 2 I N C H 13.2m m D I G I T

lattice 1996

Contextual Info: ispLSI and pLSI 2128 ® High-Density Programmable Logic Functional Block Diagram Output Routing Pool ORP Output Routing Pool (ORP) D7 D3 D5 fmax = 100 MHz Maximum Operating Frequency tpd = 10 ns Propagation Delay TTL Compatible Inputs and Outputs Electrically Erasable and Reprogrammable

isplsi device layout

Contextual Info: Lattice Features ispLSr and pLSI’ 2032 High Density Programmable Logic Functional B lock Diagram • HIGH DENSITY PROGRAMMABLE LOGIC — — — — — 1000 PLD Gates 32 I/O Pins, Two Dedicated Inputs 32 Registers High Speed Global Interconnect Wide Input Gating for Fast Counters, State

5836x

Abstract: LTC-5836G LTC-5836 LTC5836R
Contextual Info: L ü L J Ü Ü U L j Lj Ü FEA TU RES • 0.52 INCH 13.2m m D IG IT H EIG H T . • C O N T IN U O U S U N IF O R M SEG M EN T S. • CH O IC E OF S IX B R IG H T C O LO R S-R ED /BR IG H T R ED / G R E E N /Y E L LO W /O R A N G E /H IG H E F F IC IE N ­

LTML

Abstract: pbp 205 diode ltml3 kbpc 5040
Contextual Info: 1.ITE-0N L I T E 31E ? ] SS3b3b7 i QQOiaflfl PLASTIC SIDE LOOK TRANSMISSIVE SWITCHES INC R LTH-301A - ; T ILTN 3 V FEA T U R E S • NON-CONTACT SW ITCH IN G . • FO R D IR E C T PC BO A R D S O C K E T M OUNTING. • F A S T SW ITCH IN G S P EED OR D U A L-IN -LIN E

705b32

Abstract: HC05 PROGRAM DEMO CODE L16 eeprom HC08 code example HC05 HC08 freescale 08 prog 705B5 805P18
Contextual Info: Freescale Semiconductor, Inc. Freescale Semiconductor, Inc. MCUezSW0508/D FEBRUARY 1998 SOFTWARE RELEASE GUIDE FOR THE MOTOROLA MCUez  MMDS OR MMEVS HC05/08 SOFTWARE APPLICATION PACKAGE MOTOROLA Inc., 1997-1998 All Rights Reserved Important Notice to Users

Contextual Info: Lattice' ispLSr and pLSr 1048C | Semiconductor I Corporation High-Density Programmable Logic Features Functional Block Diagram HIGH-DENSITY PROGRAMMABLE LOGIC — 8000 PLD Gates — 96 I/O Pins, 12 Dedicated Inputs, 2 Global Output Enables — 288 Registers

Contextual Info: Lattice ispLSI' and pLSF 2064 Semiconductor • • m Corporation High Density Programm able Logic Features Functional Block Diagram • HIGH DENSITY PROGRAMMABLE LOGIC — 2000 PLD Gates — 64 I/O Pins, Four Dedicated Inputs — 64 Registers — High Speed Global Interconnect

0212-80B-isp1048

Abstract: 1048E 1048-80L
Contextual Info: ispLSI 1048 In-System Programmable High Density PLD Functional Block Diagram Output Routing Pool E7 E6 E5 E4 E3 E2 E1 E0 Output Routing Pool A0 D Q A1 A2 A3 A4 S Output Routing Pool F7 F6 F5 F4 F3 F2 F1 F0 Logic Global Routing Pool GRP A5 Array D Q D Q

Contextual Info: ispLSI and pLSI 1048 ® High-Density Programmable Logic Functional Block Diagram Output Routing Pool E7 E6 E5 E4 E3 E2 E1 E0 S Output Routing Pool F7 F6 F5 F4 F3 F2 F1 F0 D Q A2 A3 A4 Logic Global Routing Pool GRP Array ES Output Routing Pool A0 A1 A5

Contextual Info: Specifications ispLSI and pLSI 1048 ispLSI and pLSI 1048 ® High-Density Programmable Logic Functional Block Diagram Output Routing Pool E7 E6 E5 E4 E3 E2 E1 E0 S Output Routing Pool F7 F6 F5 F4 F3 F2 F1 F0 D Q A2 A3 A4 Logic Global Routing Pool GRP Array

Contextual Info: Specifications ispLSI and pLSI 1032 ispLSI and pLSI 1032 ® High-Density Programmable Logic Functional Block Diagram IG N Output Routing Pool D7 D6 D5 D4 D3 D2 D1 D0 ES A1 A2 Logic A3 D Array A4 C5 D Q D Q GLB C4 C3 D Q A5 C2 A6 C1 EW Output Routing Pool