.35 MICRON GATE ARRAY Search Results

TC140G44

Abstract: TC140G27 toshiba tc140g
Contextual Info: TOSHIBA TO SH IB A A M E R IC A ELECTRO NIC C O M P O N E N T S , INC. 1.0 micron TC140G CMOS Gate Array Description Features The TC140G series of 1.0 micron gate arrays has a 0.4ns gate speed and up to 172K raw gates. — Provides a 35% reduction in delay times compared to

nec d 588

Abstract: nec naming rule nec product naming rule NEC CMOS-4
Contextual Info: CMOS-9 3.3-VO LT, 0 .35-MICRON CMOS GATE ARRAYS NEC NEC Electronics Inc. Preliminary March 1995 Description Figure 1. CMOS-9 Package Examples; BGA and QFP NEC's CMOS-9 gate array family provides designers with the performance capabilities and features required

Contextual Info: Preliminary IIIÌMÌIII AffHSl September 1989 OPEN ASIC DATASHEET MAF GATE ARRAY SERIES 1.2 MICRON CMOS FEATURES . . . . . . HIGH LOAD DRIVE CAPABILITY EXCEEDING 35 mA • GATE COUNTS : 250 AND 800 . WIDE PACKAGE RANGE . EXCELLENT FOR FUSE PROGRAMMABLE ARRAYS AND BIPOLAR LOGIC REPLACE­

Contextual Info: TOSHIBA ASIC TO S H IB A A M E R IC A ELECTRO NIC C O M P O N E N T S , INC. CMOS ASIC 1C120G SERESGITE /«RAY Toshiba Corporation has introduced a series of gate arrays that use a 1.0-micron CMOS process to reduce gate delays by 35%. Applications include consolidating high-speed circuits into a single package, especially in highperformance systems.

T157WG

Abstract: S-MOS navnet A138G2 t177 4-bit full adder using nand gates and 3*8 decoder 6 input or gate SLA1024 T161RE
Contextual Info: S-M 0 S S Y S T E M S INC 5bE J> m 7 ci3 Z eÏQ'l GG01522 fc.35 H S I 1 0 SLA1 OOOO Series HIGH SPEED CMOS GATE ARRAYS • DESCRIPTION The S-MOS SLA10000 series is a channel-less gate array manufactured on S-MOS’ state-of-the-art 0.8 micron double-metal SiCMOS process. The series consists of 11 arrays ranging from 9,000 to 101,800 usable gates and

6 input or gate

Abstract: t177 SLA847 986 t04 B8237 B8250 Series A138G2 19275 resistor ssc300 S-MOS asic
Contextual Info: S-H 0 S SYSTEMS INC SbE » • 7ei3StiOti ÜDDlM'ia 076 «SIIO SLA8000 HIGH SPEED CMOS GATE ARRAY ■ DESCRIPTION The SLA8000 Series consists of a group of 13 high speed, sea-of-gates CMOS gate arrays. The series is fabricated utilizing our state-of-the-art 1.2 micron silicon gate technology. Gate counts range from 5K to 80K

Contextual Info: SYSTEMS SLA8000 Series June 1988 VERY HIGH SPEED CHANNELLESS CMOS GATE ARRAYS D escription The SLA8000 Series consists of a group of seven very high-speed, sea-of-gates CMOS gate arrays. The series is fabricated utilizing our state-of-the-art 1.2 micron sili­

tc140g

Abstract: TC140G37 TC140G27 TC140G54 TC140G44 TC140G12 TC140G68 toshiba tc140g27 TC140G09 TC140G18
Contextual Info: *1A’ li ' 'S/Si _ TOSHIBA 1t TOSHIBA AMERICA ELECTRONIC COMPOMEWTS, IIMC 1.0 micron TC140G CMOS Gate Array Features Description • Process: 1.0 micron drawn HC2MOS Si-gate double layer metal Raw gates: 2K to 172K Usable gates: up to 68K Gate speed: 0.4ns 2-input NAND gate, fanout - 2, tpd.

S-MOS navnet

Abstract: S-MOS asic B16c F1841
Contextual Info: DEC 2 3 i32S _ S-MOS S Y S T E M S • ■ ASIC _ A Seiko Epson Affiliate SLA9000 OCTOBER 1990 HIGH SPEED CMOS GATE ARRAYS DESCRIPTION The S-MOS SLA9000 series is a family of sea-of-gates • 1.0 micron drawn channel length N-Channel

pMOS NAND GATE

Abstract: A540B ISO-5
Contextual Info: UNIVERSAL SEMICONDUCTORS HE D ] “=131,0341 ODGQG4S 3 | T - «¿3.- //- 0 e] High Reliability Fast CMOS Gate Arrays UNIVERSAL SGMICONDUCTOR INC. FEATURES: • • • • • • • • •

B8228

Contextual Info: kfoEC S 6 Í?9C S-MOS S Y T E M ASIC S Preliminary A Seiko Epson Affiliate SLA10000 AUGUST 1990 HIGH SPEED CMOS GATE ARRAYS DESCRIPTION FEATURES The S-MOS SLA10000 series is a channeMess gate • .76 micron drawn channel length N-Channel array manufactured on S-MOS’ state-of-the-art 0.8

TC170G35

Contextual Info: TOSHIBA TC170G CMOS Gate Array 0.7fim, 5.0V ASICs The 0.7 |im, 5V TC170G allows higher system perfor­ mance and device integration with lower power than previous generation 5V gate array families Benefits • Advanced 0.7 micron CMOS process with fast 260ps gate

TTL 7466

Abstract: B8530 SLA909P SLA9000PIUS S-MOS navnet 936p T374H A161H F144-8 octal p-channel ARRAY
Contextual Info: S-Î1 0 S SYSTEMS INC SbE D • OQOlSlb 331 « S Î I O SLA9000PIUS Series CMOS HIGH SPEED GATE ARRAYS ■ DESCRIPTION The S-MOS SLA9000Plus series is a family of sea-of-gate arrays manufactured on S-MOS’ state-of-the-art 1.0 micron double-metal SiCMOS process. This series has been designed for high I/O, medium gate count designs

low power and area efficient carry select adder v

Abstract: IMPLEMENTATION of 4-BIT LEFT SHIFT BARREL SHIFTER 16 bit carry select adder 32 bit carry select adder 8 bit carry select adder full subtractor implementation using NOR gate 32 bit ripple carry adder carry select adder full subtractor circuit using nor gates BCD adder use rom
Contextual Info: MVA60000 MVA60000 Series 1.4 Micron CMOS MEGACELL ASICs DS5499 ISSUE 3.1 March 1991 GENERAL DESCRIPTION Very large scale integrated circuits, requiring large RAM and ROM blocks, often do not suit even high complexity gate arrays, such as Zarlink Semiconductors' CLA60000 series.

9C0000

Contextual Info: 128Mb: P8P Parallel PCM Features P8P Parallel Phase Change Memory PCM Features • Security – One-time programmable registers 64 unique factory device identifier bits 2112 user-programmable OTP bits – Selectable OTP space in main array – Three adjacent main blocks available for boot code

TC170G35

Abstract: TC170G TAB 173 AP TC170G45 Edison time delay CMOS GATE ARRAYs toshiba XBRL16
Contextual Info: TOSHIBA TC170G CMOS Gate Array 0.7\xm, 5.0V ASICs The 0.7 urn, 5VTC170G allows higher system perfor­ mance and device integration with lower power than previous generation 5V gate array families Benefits • Advanced 0.7 micron CMOS process with fast 260ps gate

Contextual Info: EXAR CORP il 3422618 D Ë | 3422blfl 0 0 Q 4 7 clt, 1 | EXAR CORP 91D 04796 D XR-P3000 STANDARD CELLS EXAR has developed an extensive library of fully characterized Standard Cells. XR-P3000 Standard Cells use a production-proven 3 micron, Dual-layer Metal, P-well digital technology, Dual-layer metal

Contextual Info: AMI3HS & AMI3LS Standard Cell PLLCORExxx AMERICAN MICROSYSTEMS, INC June 1999 AMI3HS & AMI3LS 0.35 micron CMOS Description The PLLCORExxx is a phase locked loop building block. This cell contains a voltage controlled oscillator VCO , an internal loop filter, and a digital phase frequency

IMI7340

Abstract: IMI7160 IMI7000 IMI7080 IMI7220 G4060 IMI712K G4000 IMI7490 IMI7620
Contextual Info: m iT O Q Q ^ A M IU f CMOS GATE ARRAY NTERNATIONAL M IC R O CIR CU ITS I NC TELEPHONE: 408 263-6300 TWX: 910 338 2032 FAX: 408 263-6571 Oxide-isolated silicon-gate process Dual level metalization Fully autoroutable 792 to 12,000 2-input NAND equivalents Up to 220 I/O connections

Contextual Info: Æ tctel - w ACT 1 Series FPGAs Features • 5V and 3.3V Families fully compatible with JEDEC specifications • Up to 2000 Gate Array Gates 6000 PLD equivalent gates • Replaces up to 50 TTL Packages • Replaces up to twenty 20-Pin PAL Packages

SGS-Thomson ball grid array

Abstract: schematics power supply satellite receiver ISB35000 ISB35083 ISB35130 ISB35166 ISB35208 ISB35279 ISB35389 ISB35484
Contextual Info: ISB35000 SERIES HCMOS STRUCTURED ARRAY PRELIMINARY DATA FEATURES F u l ly i n de p en d en t p o we r an d g roun d configurations for inputs, core and outputs. 0.5 micron triple layer metal HCMOS process featuring retrograde well technology, low resistance salicided active areas, polysilicide

fan 7320

Abstract: atmel 936 ttl buffer MG2014P MG2044P MG2142P MG2270P TM1019 radiation hard PLL OAI22 capacitance
Contextual Info: MG2RTP Radiation Hardened 0.5 Micron Sea of Gates Introduction The MG2RTP series is a 0.5 micron, array based, CMOS product family. Several arrays up to 490k cells cover all system integration needs. The MG2RTP is manufactured using SCMOS3/2RTP, a 0.5 micron drawn, 3 metal

Contextual Info: ADVANCE M IC R O N 1 MT28F016S2 V 2 MEG x 8 FLASH MEMORY FLASH MEMORY 2 MEG x 8 S m artV o ltag e SVT-II , SECTORED ERASE FEATURES • • • • • • • • Thirty-two 64KB erase blocks Programmable sector protect Deep Power-Down Mode: 10|iA MAX Second Generation SmartV oltage* Technology (SVT-II):

ACT 3 accelerator FPGAs

Contextual Info: ^ c te l Accelerator Series FPGAs: ACT 3 PCI-Compliant Family F e a tu re s • Up to 10,000 Gate Array Equivalent Gates. • Up to 250 MHz On-Chip Performance. Highly Predictable, Synthesis-Friendly Architecture Supports High-Level Design Methodologies. 100% Module Utilization with Automatic Place and Route