The recommended power-up sequence is to apply VCC first, followed by VREF, and then the digital supplies (VDD and VCCO). This ensures that the internal voltage regulators are powered up correctly.
To optimize THD+N performance, ensure that the analog and digital grounds are separated, use a low-noise power supply, and minimize the distance between the PCM1702PG4 and the analog signal sources. Additionally, use a high-quality clock source and ensure that the clock frequency is within the recommended range.
The maximum clock frequency that can be used with the PCM1702PG4 is 256 fs (where fs is the sampling frequency). However, it is recommended to use a clock frequency of 128 fs or lower to ensure optimal performance.
To configure the PCM1702PG4 for master clock mode, connect the MCLK pin to the clock source, and set the EXTCLK pin to a logic high. Additionally, ensure that the clock frequency is within the recommended range and that the clock signal is clean and stable.
The recommended layout and routing for the PCM1702PG4 involves separating the analog and digital signals, using a star-ground configuration, and minimizing the length of the analog signal traces. Additionally, use a solid ground plane and avoid routing digital signals under the analog signal traces.
PCM1702PG4 datasheet
by Texas Instruments
