The recommended power-up sequence is to apply VCC first, followed by VREF, and then the digital signals (SCLK, SDIN, and SYNC). This ensures proper initialization and prevents damage to the device.
The analog output filter should be designed to filter out the image frequencies generated by the delta-sigma modulation. A 3rd-order Butterworth filter with a cutoff frequency of around 100 kHz is recommended. The filter components should be chosen to minimize noise and distortion.
The maximum allowed capacitance on the VREF pin is 10 nF. Exceeding this value can cause instability in the internal voltage reference and affect the overall performance of the device.
The digital output data from the PCM1702P-JG is in 2's complement format. The data should be processed and formatted according to the specific requirements of the target application, such as audio playback or data acquisition.
The recommended clock frequency for the PCM1702P-JG is between 2.4 MHz and 4.2 MHz. The clock frequency should be chosen to ensure that the device operates within its specified performance parameters.
PCM1702P-JG4 datasheet
by Texas Instruments
