The recommended power-up sequence is to apply VCC first, followed by VREF, and then the digital supplies (VDD and VCCO). This ensures that the internal voltage regulators are powered up correctly.
To optimize THD+N performance, ensure that the analog and digital grounds are separated, use a low-noise power supply, and minimize the distance between the PCM1702P-KG4 and the analog signal sources. Additionally, use a high-quality clock source and ensure that the clock frequency is accurate and stable.
The maximum clock frequency that the PCM1702P-KG4 can support is 256 fs (where fs is the sampling frequency). For example, at a sampling frequency of 44.1 kHz, the maximum clock frequency would be 11.2896 MHz.
To configure the PCM1702P-KG4 for master clock mode, connect the MCLK pin to a clock source, and set the M/S pin low. The PCM1702P-KG4 will then generate the internal clock signals from the master clock input.
The recommended layout and routing for the PCM1702P-KG4 involves separating the analog and digital signal paths, using a star-ground configuration, and minimizing the length of the clock signal traces. Additionally, use a solid ground plane and avoid routing digital signals under the analog signal paths.
PCM1702P-KG4 datasheet
by Texas Instruments
