ZL301 Search Results

ZL30142GGG2

Abstract: ZL30142 GR-1244 GR-253
Contextual Info: ZL30142 SyncE SONET/SDH G.8262/Stratum 3 System Synchronizer Short Form Data Sheet February 2009 Features • Supports the requirements of ITU-T G.8262 for synchronous Ethernet Equipment slave Clocks EEC option 1 and 2 • Supports the requirements of Telcordia GR-1244

ZL30130

Abstract: Synchronous Ethernet ZL30136 GR-1244 GR-253 ZL30117 sdh markings
Contextual Info: ZL30130 OC-12/STM-4 SONET/SDH/GbE Stratum 2/3/3E System Synchronizer/SETS Short Form Data Sheet February 2008 Features Ordering Information • Supports the requirements of ITU-T G.8262 for synchronous Ethernet Equipment slave Clocks EEC option 1 and 2 •

GR-253-CORE

Abstract: ZL30119 ZL30119GGG ZL30119GGG2 "network interface cards"
Contextual Info: ZL30119 SONET/SDH Low Jitter Line Card Synchronizer Data Sheet December 2005 A full Design Manual is available to qualified customers. To register, please send an email to TimingandSync@Zarlink.com. Ordering Information ZL30119GGG 100 Pin CABGA Trays ZL30119GGG2 100 Pin CABGA*

ZL30123

Abstract: GR-253-CORE STM-16 ZL30123GGG ZL30123GGG2 "network interface cards"
Contextual Info: ZL30123 SONET/SDH Low Jitter Line Card Synchronizer Data Sheet May 2006 A full Design Manual is available to qualified customers. To register, please send an email to TimingandSync@Zarlink.com. Ordering Information ZL30123GGG 100 Pin CABGA Trays ZL30123GGG2 100 Pin CABGA*

Contextual Info: ZL30130 OC-12/STM-4 SONET/SDH/GbE Stratum 2/3/3E System Synchronizer/SETS Short Form Data Sheet February 2008 Features Ordering Information • Supports the requirements of ITU-T G.8262 for synchronous Ethernet Equipment slave Clocks EEC option 1 and 2 •

Contextual Info: ZL30159 General Purpose Clock Rate Converter Short Form Data Sheet March 2013 Features • Precision synthesizer generates any clock-rate from 1 Hz to 177.5 MHz with jitter below 1ps • Programmable digital PLL synchronize to any clock rate from 1 Hz 1 pps to 750 MHz

GR-1244-CORE

Abstract: GR-253-CORE ZL30109 ZL30109QDG ZL30109QDG1
Contextual Info: ZL30109 DS1/E1 System Synchronizer with 19.44 MHz Output Data Sheet Features November 2005 • Supports Telcordia GR-1244-CORE Stratum 4 and Stratum 4E • Supports ITU-T G.823 and G.824 for 2048 kbit/s and 1544 kbit/s interfaces • Supports ANSI T1.403 and ETSI ETS 300 011 for

9270N

Abstract: GR-1244 GR-253 GR-253-CORE STM-16 ZL30117 ZL30119 ZL30121 ZL30121GGG ZL30121GGG2
Contextual Info: ZL30121 SONET/SDH Low Jitter System Synchronizer Data Sheet May 2006 A full Design Manual is available to qualified customers. To register, please send an email to TimingandSync@Zarlink.com. Ordering Information ZL30121GGG ZL30121GGG2 Features • • Internal APLL provides standard output clock

Contextual Info: ZL30160 Four Channel Universal Clock Translator Short Form Data Sheet January 2012 Features Ordering Information • Four independent clock channels • Programmable synthesizers generate any clockrate from 1 kHz to 750 MHz • Two precision synthesizers generate clocks with

Contextual Info: ZL30153 Synchronous Ethernet Network Synchronization DPLL Short Form Data Sheet February 2012 Features • • Ordering Information ZL30153GGG 100 Pin LBGA ZL30153GGG2 100 Pin LBGA* Supports requirements of ITU-T G.8262 for Synchronous Ethernet Equipment Slave Clocks

GR-1244-CORE

Abstract: GR-253-CORE ZL30109 ZL30109QDG ZL30109QDG1 TC65D
Contextual Info: ZL30109 DS1/E1 System Synchronizer with 19.44 MHz Output Data Sheet Features November 2004 • Supports Telcordia GR-1244-CORE Stratum 4 and Stratum 4E • Supports ITU-T G.823 and G.824 for 2048 kbit/s and 1544 kbit/s interfaces • Supports ANSI T1.403 and ETSI ETS 300 011 for

ZL30102

Abstract: GR-1244-CORE ZL30102QDG ZL30102QDG1
Contextual Info: ZL30102 T1/E1 Stratum 4/4E Redundant System Clock Synchronizer for DS1/E1 and H.110 Data Sheet Features • November 2005 Synchronizes to clock-and-sync-pair to maintain minimal phase skew between an H.110 primary master clock and a secondary master clock

Contextual Info: ZL30161 Network Synchronization Clock Translator Short Form Data Sheet May 2013 Features • Ordering Information ZL30161GDG2 144 Pin LBGA Trays Fully compliant SEC G.813 and EEC (G.8262) flexible rate conversion digital phase locked loop (DPLL) Pb Free Tin/Silver/Copper

Contextual Info: ZL30112 SLIC/CODEC DPLL Data Sheet Features November 2009 • Synchronizes to 8 kHz, 2.048 MHz, 8.192 MHz or 19.44 MHz input • Provides 2.048 MHz and 8.192 MHz output clocks and an 8 kHz framing pulse • Automatic entry and exit from freerun mode on reference fail

GR-1244

Abstract: TCXO 20 MHZ ZL30143 ZL30136 CABGA msap ZL30145 ZL30106 ZL30108 ZL30112
Contextual Info: TIMING AND SYNCHRONIZATION PRODUCT CATALOG ZL30110 ZL30112 ZL30113 Rate Conversion PLLs PDH ZL30106 Line Card Synchronizers SyncE/ SONET/SDH SyncE SONET/SDH SyncE GR-1244 Stratum 4/4E G.823, G.824 PDH GR-1244 Stratum 3 G.823, G.824 System Synchronizers

GR-1244-CORE

Abstract: GR-253-CORE ZL30109 ZL30109QDG ZL30109QDG1 T110
Contextual Info: ZL30109 DS1/E1 System Synchronizer with 19.44 MHz Output Data Sheet Features April 2010 • Supports Telcordia GR-1244-CORE Stratum 4 and Stratum 4E • Supports ITU-T G.823 and G.824 for 2048 kbit/s and 1544 kbit/s interfaces Ordering Information *Pb Free Matte Tin

ZL30146

Abstract: ZL30142 DSA0022049 DPLL Network on Chip, telecom PROGRAMMABLE SYNTHESIZER
Contextual Info: SyncE SONET/SDH Line Card PLL ZL30146 PRODUCT PREVIEW Zarlink’s ZL30146 phase locked loop PLL is part of the Company’s market-leading portfolio of single-chip Synchronous Ethernet solutions. The highly integrated products allow manufacturers to easily upgrade or design networking equipment

ZL30131GGG

Abstract: ZL30131GGG2 STM-64 ZL30121 ZL30131 "network interface cards"
Contextual Info: ZL30131 OC-192/STM-64 SONET/SDH/10GbE Network Interface Synchronizer Short Form Data Sheet July 2009 Features • Ordering Information Synchronizes to standard telecom or Ethernet backplane clocks and provides jitter filtered output clocks for SONET/SDH, PDH and Ethernet network

GR-1244-CORE

Abstract: GR-253-CORE ZL30106 ZL30106QDG "network interface cards"
Contextual Info: ZL30106 SONET/SDH/PDH Network Interface DPLL Data Sheet Features • • • • • • • • October 2004 Synchronizes to clock-and-sync-pair to maintain minimal phase skew between inputs and outputs Supports output wander and jitter generation specifications for SONET/SDH and PDH

mt9040

Contextual Info: MT9041 1 MT9042 2 MT9043 2 MT9044 2 • • MT9045 2 • • MT9046 2 • • ZL30409 2 • • • • ZL30100 • • 2 • • ZL30101 • • 2 • • ZL30102 • • 3 • • • ZL30105 • • 3 • • • ZL30109 • • 2 • • • • • •

GR-253-CORE

Abstract: ZL30117 ZL30121 ZL30122 Compact PCI Backplane Block Diagram
Contextual Info: SONET/SDH LINE CARD SYNCHRONIZER ZL30117/22 PRODUCT PREVIEW Zarlink’s ZL30117 and ZL30122 chips are the industry’s smallest, lowest power programmable analog/digital PLLs that solve the timing challenges posed by the popular AdvancedTCA telecommunications

DSA00221054

Abstract: ZL30120 ZLAN Zarlink Semiconductor
Contextual Info: ZLAN-211 Synchronizing Ethernet Networks Using Layer 1 clocks with the ZL30120 Application Note A detailed Application Note, including test results is available to qualified customers. To register, please send an email to TimingandSync@zarlink.com. 1.0 January 2007

ZL30145

Abstract: GR-253-CORE STM16 STM-16 STM-64 DSA0022049 ZL30145GGG2
Contextual Info: ZL30145 SyncE 10 GbE SONET/SDH Rate Conversion and Jitter Attenuator PLL Short Form Data Sheet July 2009 Features Ordering Information • Can be used in systems to support the requirements of ITU-T G.8262 for synchronous Ethernet Equipment slave Clocks (EEC option 1

zl30138

Abstract: GR-1244 GR-253 ZL30117 ZL30136 ZL30138GGG2
Contextual Info: ZL30138 OC-192/STM-64 SONET/SDH/10GbE Stratum 2/3/3E System Synchronizer/SETS Short Form Data Sheet July 2009 Features Ordering Information • Supports the requirements of ITU-T G.8262 for synchronous Ethernet Equipment slave Clocks EEC option 1 and 2 •