Z803 Search Results

Z8000

Abstract: z8530 8086 logic diagram dc av converter Z8030 8086 interrupt structure 8086 structure interrupt structure of 8086 CRC-16 Z-636
Contextual Info: Z8030/Z8530 Serial Communications Controller DISTINCTIVE CHARACTERISTICS • Programmable Synchronous Modes - SDLC and HDLC, and SOLC loop supported with frame control, zero insertion and deletion, abort, a residue handling - CRC-16 and CCITT generators and checkers

rda 580 FM

Abstract: intel multibus
Contextual Info: Z8031/Z8531 Z8031/Z8531 Asynchronous Serial Communications Controller ASCC DISTINCTIVE CHARACTERISTICS • • Two 0 to 2Mbps full duplex serial channels Each channel has independent oscillator, band-rate generator, and PLL for clock recovery, dramatically

Z80 FIO

Abstract: Z8038
Contextual Info: Z8038 FIO; Z8038(F!0 128 Byte FIFO I/O Port DISTINCTIVE CHARACTERISTICS Asynchronous FIFO Interface — 128-byte FIFO provides bidirectional CPU to CPU or peripheral interface. Expandable In Length and Width — FlOs can be connected in parallel for wider words,

Z- FIO

Abstract: dcp 4 z Z8038
Contextual Info: Z I L O G INC 17E D T1ÖM043 DD1E0Ô3 T " T -S £ -3 3 -D 3 Z8038/Z8538 FIO FIFO Input/ Output Interface Unit October 1988 Features • 128-byte FIFO buffer provides asynchronous bidirectional CPU/CPU or CPU/peripheral interface, expandable to any width in byte

Z8030ACS

Abstract: Z8030APS Z8030A IN SDLC PROTOCOL USING SCC WITH Z8000 IN SDLC PROTOCOL CRC-16 Z8000 Z8030 z-scc Z8030 PS
Contextual Info: Z8030 Z8000 Z-SCC Serial Communications Controller Product Specification Zilog A pril 1985 • Two in dependent, 0 to 1.5M bit/second, fullduplex channels, eac h with a separate crystal oscillator, b a u d rate generator, a n d Digital Phase-L ocked Loop for clock recovery.

Z380

Abstract: programming z80 85230 Z8 cross assembler 18.432 mhz oscillator Z80 Programming manual Z80 Assembly Language Programming Manual z80 kit Z80 SCC z8000 manual
Contextual Info: Z8038000ZCO CPS DC-4201-00 CUSTOMER PROCUREMENT SPECIFICATION Z8038000ZCO Z80380 EVALUATION BOARD DESCRIPTION KIT CONTENTS This kit contains an assembled circuit board, software and documentation to aid evaluators and potential users in designing with the Z80380.

Contextual Info: Z8030/Z8530 H Z8030/Z8530(H) Serial C om m unications C ontroller DISTINCTIVE CHARACTERISTICS • Tw o 0 to 2 Mbps full duplex serial channels Each channel has independent oscillator, baud-rate generator, and PLL for clock recovery, dram atically reducing external com ponents.

Z853006PSC

Abstract: Z8530 Z8530A CRC-16 M043 Z8030 Z85304
Contextual Info: P r o d u c t S p e c if ic a t io n < 2 *2 iL O E Z8030/Z8530 Z -B U S S C C S E R IA L C o m m u n ic a t io n C o n t r o l l e r FEATURES • Z 8530 O p tim iz e d Microprocessors. ■ Z80300ptimizedforMultiplexed Bus Microprocessors. ■ Two Independent, 0 to 2 Mbit/Second, Full-Duplex

TXC10 M 60

Abstract: Z382 Z80382 T105 94 V0 TXC10
Contextual Info: P r e l im in a r y C u s t o m e r P r o c u r e m e n t S p e c if ic a t io n v% \ Z80382 SL1944 H ig h - P e r f o r m a n c e D a t a C o m m u n ic a t io n s P r o c e s s o r FEATURES • Embedded Z380 Microprocessor Eight Advanced DMA Channels with 24-Bit Addressing

Contextual Info: ZI LO G INC 03 D È I T T Ö M O M B □□□fllSS □ | 9984043 ZILOG INC 03E 08155 Z8030 M ilitary T-iS-Zl-oy Z8000 Z-SCC Serial Communications Controller Military Zilog Electrical Specification July 1985 FEATURES • Two independent, 0 to 1.5M bit/second, full-duplex

Z8538

Abstract: 6N37
Contextual Info: < £ 2 iL G E Product Specification 1 Z8038/Z8538 FIO FIFO input/ Output Interface Unit The Z8538 is no longer offered. Features • 128-byte FIFO buffer provides asynchronous bidirectional CPU/CPU or CPU/peripheral interface, expandable to any width in byte

Z8036APS

Abstract: Z-CIO Z8000 Z8036 Z8036A Z8036CM Z8036CS Z8036PS
Contextual Info: Z8036 Z8000 z-C10 Counter/Timer and Parallel I/O Unit Product Specification Zilog A pril 1985 General Description Two in d ep en d en t 8-bit, double-buffered, bidirectional I/O ports plus a 4-bit special-purpose I/O port. I/O ports feature program m able polarity,

c828 transistor datasheet

Abstract: C828 transistor transistor c828 c828 Z80A-CTC a684 transistor C838 transistor c828 datasheet z80a-PIO C880 transistor
Contextual Info: APPLICATION NOTE 9 SCC IN BINARY SYNCHRONOUS COMMUNICATIONS 9 INTRODUCTION Zilog’s Z8030 Z-SCC Serial Communications Controller is one of a family of components that are Z-BUS compatible with the Z8000 CPU. Combined with a Z8000 CPU or other existing 8- or 16-bit CPUs with nonmultiplexed buses

Z803U

Contextual Info: page 1 2 3 4 5 6 7 8 9 10 11 12 13 Z803U sheet 1 2 3 4 5 6 7 8 9 A B C FP date 1960.11.11 1960.11.11 1960.11.11 1960.11.11 1960.11.11 1960.11.11 1960.11.11 1960.11.11 1960.11.11 1960.11.11 1960.11.11 1960.11.11 2000.01.14

Z80 FIO

Abstract: z bus Z8038-FIO z-scc cpu 226 z-fio D-40 Z8000 Z8036 Z8038
Contextual Info: Z8038 FIO Z8038(FI0) 128 Byte FIFO I/O Port DISTINCTIVE CHARACTERISTICS Pattern m atching logic on chip — FIO can detect a data pattern and interrupt CPU. B yte count available to softw are — An on-chip register which contains the actual num­ ber o f bytes in the FIFO can be read by the soft­

HS 153 SP

Abstract: Z8038-FIO Z8038 Z80 FIO Z8038 D6 Z80 -Z-SCC amd 8085 30BC Z8038 AMD PF0012
Contextual Info: Z8038 FIO Z8038(FI0) 128 Byte FIFO I/O Port DISTINCTIVE CHARACTERISTICS Asynchronous FIFO Interface — 128-byte FIFO provides bidirectional CPU to CPU or peripheral interface. Expandable In Length and Width — FIOs can be connected in parallel for wider words,

Contextual Info: f Z 7 ^ 7# S G S -T H O M S O N [ » [ f g m i O T M t f l « _Z 8 0 3 8 Z-FIO/FIFO INPUT/OUTPUT INTERFACE UNIT DESCRIPTIO N The Z8038 FIO FIFO Input/Output Interface Unit is a 128-byte buffer that interfaces two CPUs or a CPU and a peripheral device. Multiple FIOs can be

Z80 Programming manual

Abstract: z80 kit Z380 cmos cross manual 18.432 mhz oscillator programming z80 Z80 Assembly Language Programming Manual z8000 manual Z80 SCC Z80380
Contextual Info: Z8038000ZCO S UPPOR TP RODUCT Z8038000ZCO Z80380 EVALUATION BOARD DESCRIPTION KIT CONTENTS This kit contains an assembled circuit board, software and documentation to aid evaluators and potential users in designing with the Z80380. Z80380 Evaluation Board

CRC-16

Abstract: z8530 baud rate converter Z8030 baud rate generator Z803
Contextual Info: Z8030/Z8530 Z8030/Z8530 Z-BUS SCC/SCC SERIAL COMMUNICATIONS CONTROLLER GENERAL DESCRIPTION The SCC Serial Communications Controller is a dualchannel, multi-protocol data communications peripheral designed for use with conventional non-multiplexed buses and the Zilog Z-Bus®. The SCC functions as a serial-toparallel, parallel-to-serial converter/controller. The SCC

Z80382

Abstract: Z8038200ZCO
Contextual Info: Z8038200ZCO Evaluation Kit Product Brief 1 Z8038200ZCO FEATURES • • • Configurable for ISA/AT, PCMCIA, or Standalone Operating Modes Debug Monitor in EPROM Includes the Following: – Download Hex File from PC – Display/Compare/Fill/Edit Memory Data

ZS040

Abstract: ZS-040 Z8038D6 l8038 Z8001 package size Z8038D1 Z8060-FIFO z bus Z8038 Z80 FIO
Contextual Info: SGS-THOMSON Z8038 Z-FIO/FIFO INPUT/OUTPUT INTERFACE UNIT DESCRIPTIO N The Z8038 FIO FIFO Input/Output Interface Unit is a 128-byte buffer that interfaces two CPUs or a CPU and a peripheral device. Multiple FIOs can be used to create a 16-bit or wider data path, or two

z08030

Abstract: TDA 2020 Application Z0803006CME Z0803004CMB z0803006 M/TDA 2016 Z08030-04CMB TDA 2020 z080300
Contextual Info: | ¿ illO y Z8030 Military Z8000 Z-SCC Serial Communications Controller Military Electrical Specification D ecem ber 1989 FEATURES • Two independent, 0 to 1.5M bit/second, full-duplex channels, each with a separate crystal oscillator, baud rate generator, and Digital Phase- Locked Loop for clock

Z84C00

Abstract: Z8038000ZAS Z80380
Contextual Info: Z8038000ZAS CPS DC-4220-00 CUSTOMER PROCUREMENT SPECIFICATION Z8038000ZAS Z80380 ASSEMBLER, LINKER AND LIBRARIAN GENERAL DESCRIPTION The Z80380 Macro Assembler Requirements The Z80380 Macro Assembler ZASM generates relocatable object code modules in IEEE 695 OMF format.

Contextual Info: Zilog P ro d u c t S p e c if ic a t io n Z8036 Z8000 Z-CIO Counter/Timer and Parallel I/O Unit October 1988 Features General Description • Two independent 8-bit, double-buffered, bidirectional I/O ports plus a 4-bit special-purpose I/O port. I/O ports