YJA 9 Search Results

AADV

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Contextual Info: ALLEGRO MICROSYSTEMS INC =13 D • 0S0433Ö 0G037M7 □ ■ A L GR T-91-01 PROCESS YFA Process YFA NPN Power Darlington Transistor Process YFA is a double-diffused epitaxial planar N P N silicon Darlington pair. It is designed for use in high-gain, high-power amplifiers. Its complement is

Contextual Info: SK25GAD063T C- R PO S$@ 407,- %*8,23.-, -', .6.,+ Absolute Maximum Ratings Symbol Conditions IGBT T$LA CU R PO S$ E$ CU R XPO S$ E$[¥ *'-) MWW T NW Y C- R ZW S$ PX Y MW Y ] PW T XW a- E$[¥R P : E$0%& T$$ R NWW T^ TFL _ PW T^ T$LA ` MWW T Inverse Diode IGBT Module

yja 9

Abstract: f41 marking
Contextual Info: SCI7700YSeries/SCI7701 YSeries CMOS VOLTAGE DETECTOR • DESCRIPTION The SCI7700YSeries/SCI7701 YSeries are a series of low-power precision voltage detectors, which do not require external adjustments. The SCI7700YSeries/SCI7701 YSeries have such applications as battery-life

4609

Contextual Info: 4609 TRIODE for use in téléphoné equipment TRIODE pour utilisation en équipement téléphonique TRIODE zur Verwendung in Telephon-Anlagen Heating Chauffage: Heizung :direct by D.C.; series or parallel supply direct par C.C.; Vf alimentation en série ou

Contextual Info: PRELIMINARY MICZRON I 16 MEG X 4 FPM DRAM H R AM LSHMIVI MT4LC16M4A7 MT4LC16M4T8 FEATURES PIN ASSIGNMENT Top View • Single +3.3V ±0.3V power supply • Industry-standard x4 pinout, timing, functions and packages • 13 row, 11 column addresses (A7) 12 row, 12 column addresses (T8)

RE LOG 2 TZ 11

Abstract: "halbleiterwerk frankfurt" halbleiterwerk Halbleiterwerk Frankfurt ddr veb VEB Halbleiterwerk Frankfurt scans-048 Frankfurt Oder L192A1A2 Deutschen Demokratischen Republik
Contextual Info: V o rlä u fig e S c h a ltk re is DL 192 D DL 193 D D ie der L o w -Pow er~ Sch o ttk y-T echn o log ie der b eiden Z ä h lim p u ls e B e id e Z ä h le r M it ja te n e in g ä n g e n vorw ärts e in e s TV w ird davon vo rw ä rts b e stim m t, und TR

Contextual Info: M IC R O N 512K 512K X MT20D51240 40 DRAM MODULE 40 DRAM FAST PAGE MODE MT20D51240 LOW POWER, EXTENDED REFRESH (MT20D51240 L) FEATURES • • • • • • • • • PIN ASSIGNMENT (Top View) 72-pin single-in-line package High-performance, CMOS silicon-gate process.

MT8D132G-6

Abstract: MT4C4001
Contextual Info: I^ i c r o n 1 MEG DRAM _ _ _ _ _ _ _ 1 MEG x 32, 2 MEG x 16 _ FAST PAGE MODE MT8D132 LOW POWER, F EXTENDED Y T P M n F n RF REFRESH (MT8D132 L) MODULE 1 •1 MT8D132 32, 2 MEG x 16 DRAM M O D ULE X 1- ^ V / k . L . FEATURES • Industry-standard pinout in a 72-pin single-in-line

WTS 1.7 IC 28 PIN

Abstract: wts 28 pin ic
Contextual Info: ADVANCE I^ IIC R O N 4 MEG DRAM MODULE 4 MEG X X MT10D440 40 DRAM MODULE 40 DRAM FAST-PAGE-MODE • • • • • Industry-standard 72-pin single in-line package High-performance CMOS silicon-gate process Single 5V ±10% power supply All device pins TTL-compatible

Contextual Info: MICRON MT8D1 32 S l MT16D232(S) 1 MEG, 2 MEG x 32 DRAM MODULE TSCHNOLOO. INC DRAM 1 MEG, 2 MEG x 32 n n r\r\n t c 4>8 m e g a b yte s, sv, f a s t page mode, OPTIONAL SELF REFRESH IVIUUULE FEATURES PIN ASSIGNMENT (Front View) • JEDEC- and industry-standard pinout in a 72-pin,

Contextual Info: 4, 8 MEG X 36 PARITY DRAM SIMMs MICRON I TECHNOLOGY. INC. QRAM LSI l i b i v i MODULE MT12D436 MT24D836 FEATURES • JEDEC- and industry-standard pinout in a 72-pin, single in-line memory module SIMM • 16MB (4 Meg x 36) and 32MB (8 Meg x 36) parity versions

t3d19

Abstract: MT4C1024DJ a7020
Contextual Info: [MICRON □PAM _ _ _ _ . . _ 1 MEG X MT3D19 9 DRAM MODULE 1 MEG x 9 DRAM _ FAST-PAGE-MODE MT3D19 LOW POWER, EXTENDED REFRESH (M T3D19 L) MODULE \J L. t . IVIv y U FEATURES PIN ASSIGNMENT (Top View) • Industry-standard pinout in a 30-pin single-in-line

Contextual Info: MT9D49 MICRON I 4 MEG X 9 DRAM MODULE TECHNOLOGY INC. DRAM MODULE 4 MEG x 9 4 MEGABYTE, 5V, FAST PAGE MODE FEATURES • JEDEC- and industry-standard pinout in a 30-pin single-in-lme m emory module SIMM • High-perform ance CM OS silicon-gate process • Single 5V ±10% power supply

Contextual Info: M IC R O N 4 MEG 4 MEG DRAM MODULE X X 8 MT8D48 DRAM MODULE 8 DRAM FAST-PAGE-MODE (MT8D48 LOW POWER, EXTENDED REFRESH (MT8D48 L) FEATURES PIN ASSIGNMENT (Top View) • In d u stry -sta n d a rd p in o u t in a 3 0 -p in sin gle-in -lin e p ack ag e • H ig h -p erfo rm a n ce C M O S silico n -g ate p ro cess

Contextual Info: NST30010MXV6T1G, NSVT30010MXV6T1G Dual Matched General Purpose Transistor PNP Matched Pair http://onsemi.com These transistors are housed in an ultra−small SOT563 package ideally suited for portable products. They are assembled to create a pair of devices highly matched in all parameters, eliminating the need

Contextual Info: MICRON I 128K X TECHNOLOGY, INC. MT58LC128K16/18B3 16/18 SYNCBURST SRAM 128Kx 16/18 SRAM SYNCHRONOUS SRAM +3.3V SUPPLY, FLOW-THROUGH AND SELECTABLE BURST MODE FEATURES • • • • • • • • • • • • • • • • Fast access times: 8.5, 9,10 and 11ns

pnp matched pair

Abstract: NSVT30010MXV6T1G NST30010MXV
Contextual Info: NST30010MXV6T1G, NSVT30010MXV6T1G Dual Matched General Purpose Transistor PNP Matched Pair http://onsemi.com These transistors are housed in an ultra−small SOT563 package ideally suited for portable products. They are assembled to create a pair of devices highly matched in all parameters, eliminating the need

1024x8 memory

Contextual Info: PRELIMINARY 8 MEG x 8 EDO DRAM l^ ic iR o r s j MT4LC8M8P4 MT4LC8M8C2 DRAM FEATURES • Single +3.3V ±0.3V power supply • Industry-standard x8 pinout, timing, functions and packages • 12 row, 11 column addresses C2 or 13 row, 10 column addresses (P4)

DM-01

Abstract: Techno RC
Contextual Info: MT2D18 1 MEG x 8 DRAM MODULE I^ IC R O N REFRESH _ Returning RAS and CAS HIGH terminates a m emory cycle and decreases chip current to a reduced standby level. A lso, the chip is preconditioned for the next cycle during the RAS HIGH time. M emory cell data is retained in its

Contextual Info: M 1, 2 MEG X 32 DRAM SIMMs IC R O N D R A M l^ ri V I MT2DT132(X MT2D132(X) MODULE IV IU U U L U MT4DT232D(X) MT4D232D(X) FEATURES PIN ASSIGNMENT (Front View) • JEDEC- and industry-standard pinout in a 72-pin, single in-line memory module (SIMM) • 4MB (1 Meg x 32) and 8MB (2 Meg x 32)

MT58LC64K18B2

Contextual Info: ADVANCE l^ iiC R o r s i 64K X MT58LC64K18B2 18 SYNCHRONOUS SRAM 64K x 18 SRAM +3.3V SUPPLY W ITH CLOCKED, REGISTERED INPUTS AND BURST COUNTER FEATURES PIN ASSIGNMENT Top View • • • • • • • • • • Fast access times: 9 ,1 0 ,1 2 and 17ns

Contextual Info: MT8D48 4 MEG X 8 DRAM MODULE MICRON I TECHNOLOGY. INC DRAM MODULE 4 MEG X 8 4 MEGABYTE, 5V, FAST PAGE MODE FEATURES • JEDEC- and industry-standard pinout in a 30-pin single-in-line m emory module SIMM • High-perform ance CM OS silicon-gate process • Single 5V ±10% power supply

Contextual Info: M ir ~ P r i M I 11 ^ MT5C64K16A1 RE VO LUT IO NA RY PINOUT 64K x 16 SRAM SRAM 64K X 1 6 SRAM FEATURES • Fast access times: 1 2 ,1 5 ,2 0 and 25ns • Fast output enable access time: 6, 8 ,1 0 and 12ns • Multiple center power and ground pins for improved