Y26 DATA SHEET Search Results

Contextual Info: VSC838 Data Sheet FEATURES ● 36 Input by 36 Output Crosspoint Switch ● 66MHz Dual Programming Port ● 3.2Gb/s NRZ Data Bandwidth ● Parallel and Serial Programming Modes ● Non-Blocking Architecture Broadcast and Multicast Capabilities ● Programmable On-Chip I/O Termination

AC13

Abstract: TMS320C44 C1D5 AA23
Contextual Info: SPRU177 Data Sheet Addendum DATE: August 1996 Document Addendum: GFW Plastic Ball Grid Array Package This addendum is being added to the TMS320C44 Digital Signal Processor Data Sheet. Literature Number Being Updated: SPRS031B This Data Sheet Addendum SPRU177 ships with the TMS320C44 Digital Signal Processor Data Sheet.

LSI SPLC780A

Abstract: COM161 Y801 SPLC063 DL246 Y80-1 SPLC063A SPLC100 Y13410 splc780
Contextual Info: SPLC063A 80-CHANNEL SEGMENT LCD DRIVER GENERAL DESCRIPTION The SPLC063A is a LCD driver LSI which is fabricated by low power CMOS technology. Basically it consists of two set of 40-bit bi-directional shift registers, 40 data latch flip-flops and 40 liquid crystal display driver circuits. It

ztx a11

Abstract: PES24NT3 PCIE SWITCH IDT 89HPES24NT3 IDT M22
Contextual Info: 89HPES24NT3 Data Sheet 24-Lane 3-Port Non-Transparent PCI Express Switch Preliminary Information* ® Device Overview Flexible Architecture with Numerous Configuration Options – Port arbitration schemes utilizing round robin – Supports automatic per port link width negotiation x8, x4, x2,

Contextual Info: SPLC100A3 40-Channel SEG/COM LCD Driver Preliminary JUL. 02, 2002 Version 0.1 SUNPLUS TECHNOLOGY CO. reserves the right to change this documentation without prior notice. Information provided by SUNPLUS TECHNOLOGY CO. is believed to be accurate and reliable.

Contextual Info: DATA SHEET MOS INTEGRATED CIRCUIT µPD98501 NETWORK CONTROLLER The µPD98501 is a high performance controller which can perform the protocol conversion between IP packets and ATM cells, which is especially suitable for ADSL modem. It includes high performance MIPS based 64-bit

DBL 1052

Contextual Info: r 3 PRODUCT NUMBER SEE TA B LE -, 100/2. 54 • >i I > i l ¡§I8 lít í 5 3 *4u* rI* C o Ui _. 20 0_ 5, 08 |i Ì 5 JL 5 5“ . 276 7, 01 . 310 7, 87 £? t : u a A t-3 ï—0-£ _ 013 REF. I ' J J Ù L s : tf Ï4 4 IÍ +. 015 005 38 1 , 02 -, 13 040 . 1052. 67

PR79A

Abstract: PR65A PR83a PR88A PR97A PR74A pr41a PR50A ASP-122953-01 PR91A
Contextual Info:  LatticeECP3 I/O Protocol Board to Texas Instruments ADC/DAC Adapter Board User’s Guide May 2010 Revision: EB54_01.2  Lattice Semiconductor LatticeECP3 I/O Protocol Board to Texas Instruments ADC/DAC Adapter Board User’s Guide Introduction The LatticeECP3 I/O Protocol Board to TI ADC/DAC Adapter provides a convenient platform to evaluate, test

Contextual Info: DATA SHEET MOS INTEGRATED CIRCUIT µPD98502 NETWORK CONTROLLER The µPD98502 network controller is an LSI for network terminal applications such as ADSL systems. The controller integrates a VR4120A MIPS RISC CPU core, memory interface, PCI, and other network interface

WS59032

Abstract: 32X32 IA59032 Waferscale Integration 8 BIT ALU IC RAM31
Contextual Info: Page 1 of 17 IA59032 32-Bit High Speed Microprocessor Slice Data Sheet FEATURES • Eight CMOS 2901 Type Devices in a Single Package • 32 x 32 Dual Port RAM • High Speed Operation - 23MHz Read-Modify-Write Cycle • Fully Firmware Compatible with the 2901

280-pin

Contextual Info: Includes MAX 9000A MAX 9000 Programmable Logic Device Family May 1999» ver. 6 Features Data Sheet ^ $ $8 M ffl M $8 j&j &£ 88 ^ High-performance CMOS EEPROM-based programmable logic devices PLDs built on third-generation Multiple Array MatriX (MAX®) architecture

AE12AE13

Contextual Info: QL7160 QuickDSP Data Sheet • • • • • • Combining Embedded DSP Blocks, Performance, Density, and Embedded RAM 1.0 Device Highlights Clock Network High Speed Customizable Logic • 9 global clock networks • 0.25u, 5 layer metal CMOS process • 1 dedicated, 8 programmable

AF14

Abstract: EPM9320 EPM9560
Contextual Info: Includes MAX 9000A MAX 9000 Programmable Logic Device Family November 2001, ver. 6.3 Features. Data Sheet • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ High-performance CMOS EEPROM-based programmable logic devices PLDs built on third-generation Multiple Array MatriX

epm9320

Abstract: AF14 EPM9560
Contextual Info: Includes MAX 9000A MAX 9000 Programmable Logic Device Family December 2002, ver. 6.4 Features. Data Sheet • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ High-performance CMOS EEPROM-based programmable logic devices PLDs built on third-generation Multiple Array MatriX

diode marking code e26

Abstract: PIN DIAGRAM of IC AD 524 ultrasparc
Contextual Info: S un M ic r o e l e c t r o n ic s July 1997 U2P DATA SHEET UPA to PCI Interface D e s c r ip t io n The U2P * chip is the primary connection on an UltraSPARC CPU board between the UPA System Bus including UltraSPARC Processors and Memory and a PCI based I/O Subsystem. Its major functions are

UltraSPARC-IIIi

Abstract: NVRAM for Sun UltraSparc IIi UltraSPARC-III STP2003QFP 4900 H02 gigabyte MOTHERBOARD CIRCUIT diagram A27 639 SME2411 SME1430LGA-360 SME1430LGA-440
Contextual Info: SME1430LGA-360 SME1430LGA-440 SME1430LGA-480 May 1999 UltraSPARC -IIi CPU DATA SHEET Highly Integrated 64-Bit RISC; L2-Cache, DRAM, PCI Interfaces DESCRIPTION The SME1430LGA CPU UltraSPARC-IIi microprocessor is a highly-integrated, 64-bit, SPARC V9 superscalar

Contextual Info: 80960RP 1.0 1.2 ABOUT THIS DOCUMENT Terminology In this document, the following terms are used: This data sheet contains ADVANCE INFORMATION about Intel’s i960 RP processor, including a func­ tional overview, mechanical data package signal locations and simulated thermal characteristics ,

AD143

Abstract: PPC405GP powerpc 405gp y51 h 120c IBM powerpc 405gp IBM25PPC405GP-3BE266C transistor af18 405GP PC-100 SA12E
Contextual Info: PowerPC 405GP Embedded Processor Data Sheet Features • IBM PowerPCTM 405 32-bit RISC processor core operating up to 266 MHz • PC-100 Synchronous DRAM SDRAM interface operating up to 133 MHz - 32-bit interface for non-ECC applications - 40-bit interface serves 32 bits of data plus 8

Contextual Info: microelectronics Preliminary Data Sheet November 1998 group Lucent Technologies Bell Labs Innovations TFRA08C13 Octal T1/E1 Framer Features Facility Data Link Features • Eight independent T1/E1 transmit and receive framers. m Internal DS1 transmit clock synthesis—no external

XC95288

Abstract: BG352 HQ208 XC9500 X5906 X7131 HQ208I
Contextual Info: 1 XC95288 In-System Programmable CPLD  December 4, 1998 Version 3.0 1 1* Product Specification Features Power Management • • 15 ns pin-to-pin logic delays on all pins fCNT to 95 MHz • • • 288 macrocells with 6,400 usable gates Up to 192 user I/O pins

QL6250-4PQ208C

Contextual Info: QL6250 Eclipse Data Sheet • • • • • • Combining Performance, Density and Embedded RAM 1.0 Device Highlights Flexible Programmable Logic • .25u, 5 layer metal CMOS process Advanced Clock Network • 9 Global Clock Networks • 2.5 V Vcc, 2.5/3.3 V drive capable I/O

XC95288

Contextual Info: flXIU N X XC95286 In-System Programmable CPLD October 28, 1997 Version 2.0 Preliminary Product Specification Features MC h p (1.7) + MC lp (0.9) + MC (0.006 m A/M Hz) f • 15 ns pin-to-pin logic delays on all pins Where: • • • • fcNT to MHz 288 macrocells with 6,400 usable gates

LSISAS1068

Abstract: LSISASx12 LSI Logic SAS controller chip I2C sas SFF8485 PAR64 SFF-8485 TX6 RX6 JZ02-000015-00 M4G-21
Contextual Info: LSISAS1068 8-Port, 3 Gbit/s Serial Attached SCSI Controller Datasheet Version 2.0 The LSISAS1068 is an eight, port 3.0 Gbit/s SAS/SATA controller that is compliant with the Fusion-MPT architecture, provides a PCI-X interface, and supports Integrated RAID.

Contextual Info: DATA SHEET MOS INTEGRATED CIRCUIT µPD98431 10/100 Mbps Ethernet TM CONTROLLER DESCRIPTION The µPD98431 is a 10/100 Mbps Ethernet controller having eight Media Access Control MAC ports conforming to IEEE 802.3 and IEEE 802.3u. Each port can store 1 packet of receive data since each port has a 2 KB receive FIFO. This can reduce the