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SASI

Abstract: cmps a13 grd 07 z32106 Z32100 IRR28 we32100
Contextual Info: Zilog P roduct S pecification January 1987 / O D ^ O ^ Z32106 M A U M A T H A C C E L E R A T IO N U N IT DESCRIPTION T he Z32106 M ath A cceleration U nit M AU provides floating-point capability fo r the Z32100 M icroprocessor and is fully com patible with

Contextual Info: Advanced Micro Devices A m 2 8 F 0 1 0 131,072 x 8-Bit CMOS Flash Memory DISTINCTIVE CHARACTERISTICS I High perform ance - 90 ns m aximum access tim e Latch-up protected to 100 mA from -1 V to Vcc +1 V • CM OS Low pow er consum ption - 30 m A m aximum active current

82801DB

Abstract: E8870DH intel 4002 W32 MARKING 82802AC 82870P2 E8870 E8870IO E8870SP P64H2
Contextual Info: Intel E8870IO Server I/O Hub SIOH Datasheet Product Features • ■ ■ ■ ■ ■ ■ Scalability Port (SP): — Two SPs with 3.2 GB/s peak bandwidth per direction per SP. — Bi-directional SPs for a total bandwidth of 12.8 GB/s. Four Hub Interface 2.0 Ports:

diode E1110

Abstract: lN4002 LN4003 ANA 618 20010 TDB 0123 km b3170 E1110 Diode UB8560D MAA723 moc 2030
Contextual Info: elektronik-bauelem ente I WT VD AVL 1 /8 7 Bl. 2 E r l ä u t e r u n g e n z u m I n h a l t und zu d e n A n g a b e n d e r B a u e l e m e n t e - V e r g l e i c h s l i s t e D ie B a u e l e m e n t e - V e r g l e i c h s l i s t e e n t h ä l t a l l e in d e r B i l a n z v e r a n t w o r t u n g d e s V E B K o m b i n a t

80486DX2 microprocessor

Contextual Info: P R E L IM IN A R Y a Am486 DX2 3.3-Volt Processor High-Performance, Clock-Doubled, 32-Bit Microprocessor Advanced Micro Devices DISTINCTIVE CHARACTERISTICS • Complete 32-Bit Architecture ■ Operating voltage range 3.3 V ± 0.3 V — Address and data buses

Contextual Info: Data Sheet August 1996 mi c r o e l e c t r o n i c s gr oup Lucent Technologies Bell Labs Innovations • Four 10 Mbits/s Ethernet transceivers and MACs integrated together with separate transmit and receive port FIFOs and a single DMA interface simplity the design of a frame-switching hub. Each

HM534253BT

Abstract: HM534
Contextual Info: ADE-203-204B Z HM534253B Series 262,144-word x 4-bit Multiport CMOS Video RAM Rev. 2.0 Dec. 8, 1994 HITACHI The HM534253B is a 1-Mbit multiport video RAM equipped with a 256-kword x 4-bit dynamic RAM and a 512-word x 4-bit SAM (serial access memory). Its R A M and SA M operate

Contextual Info: MOTOROLA Order this document by MCM67H618B/D SEMICONDUCTOR TECHNICAL DATA MCM67H618B Product Preview 64K x 18 Bit BurstRAM Synchronous Fast Static RAM With Burst Counter and Self-Timed Write The MCM67H618B is a 1,179,648 bit synchronous fast static random access

Contextual Info: DATA SHEET MOS INTEGRATED CIRCUIT /XPD 431536L 1M-BIT CMOS SYNCHRONOUS FAST SRAM 32K-WORD BY 36-BIT FLOW THROUGH OPERATION Description The ,uPD431536L is a 32,768-word by 36-bit synchronous static RAM fabricated with advanced CMOS technology using N-channel four-transistor memory cell.

Contextual Info: DATA SHEET MOS INTEGRATED CIRCUIT jU P D 4 3 1 5 3 2 L 1M-BIT CMOS SYNCHRONOUS FAST SRAM 32K-WORD BY 32-BIT FLOW THROUGH OPERATION Description The ,uPD431532L is a 32,768-word by 32-bit synchronous static RAM fabricated with advanced CMOS technology using N-channel four-transistor memory cell.

Contextual Info: DATA SHEET MOS INTEGRATED CIRCUIT /XPD 431532L 1M-BIT CMOS SYNCHRONOUS FAST SRAM 32K-WORD BY 32-BIT FLOW THROUGH OPERATION Description The ,uPD431532L is a 32,768-word by 32-bit synchronous static RAM fabricated with advanced CMOS technology using N-channel four-transistor memory cell.

Contextual Info: AT&T Data Sheet October 1995 Microelectronics Optimized Reconfigurable Cell Array ORCA 2C Series Field-Programmable Gate Arrays Features Description • High-performance, cost-effective 0.5 |im technology (four-input look-up table delay less than 3.6 ns)

Contextual Info: Data Sheet September 1995 = m A TsJ Microelectronics DSP1616-x30 Digital Signal Processor 1 Features 2 Description • Optimized for digital cellular applications with a bit manipulation unit for higher signal coding efficiency ■ 20 ns, 25 ns, and 30 ns instruction cycle times

SKHI 65

Abstract: CAT64LC40 SKHI 10 op
Contextual Info: bûE nt.Hb'ìS □0D17SM DäT » Advance CST CATALYST S EM ICO NDUC TOR S E M I C O N D U C T O R CAT64LC40/CAT64LC40I 4K-Bit SERIAL E2PROM FEATURES • SP I Bus C o m p atib le P o w er-U p In a d v e rtan t W rite P rotectio n ■ L o w P o w e r C M O S T e c h n o lo g y

74s188 programming

Abstract: 74S471 N82S06 74S470 dip18 package str 52100 MARKING CODE N-CHANNEL MOS FIELD EFFECT TRANSISTOR 74S472 PROM PROGRAMMING 8080a 74S287 programming instructions
Contextual Info: The E ngineering Staff of TEXAS INSTRUMENTS INCORPORATED Semiconductor Memory Data Book y for \ T exas In Design Engineers s t r u m e n t s >le of Contents • Alphanumeric Index • GENERAL INFORMATION Selection Guides • Glossary INTERCHANGEABILITY GUIDE

MCM62486

Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA MCM62486A 32K x 9 Bit BurstRAM Synchronous Static RAM With Burst Counter and Self-Timed Write The MCM62486A is a 294,912 bit synchronous sialic random access memory designed to provide a burstable, high-performance, secondary cache for the

OAOLP2

Abstract: temperature digital display JUMO Lan M smd transistor 1p7 bti ml-2 transistor SMD 1p6 transistor DK qe smd edto 116.4 8052ah basic toba 639 270645
Contextual Info: MCS@51 MICROCONTROLLER FAMILY USER’S MANUAL ORDER NO.: 272383-002 FEBRUARY 1994 Intel Corporation makes no warrsnfy for the uee of ite products and assumes no responsibility for any ewors which may appear in this document nor does it make a commitment to update the information contained herein.

Contextual Info: PRELIMINARY KM4216C258/L/F, KM4216V258/I-/F 256K 16 Bit CM OS Video RAM x FEATURES GENERAL DESCRIPTION Dual port Architecture 2S6K x 16 bits RAM port 512 x 16 bits SAM port Performance range: _ t-• —_ _ Speed Parameter — -RAM access tim e tRAC

74HC165

Abstract: 74HC165 truth table
Contextual Info: Æ T SGS-THOMSON M54HC165 M74HC165 *7# H0»[i[LI glíl i]0 Í 8-BIT PISO SHIFT REGISTER * HIGH SPEED tpD = 21 ns (TYP. at VCc = 5V • LOW POWER DISSIPATION ICC = 4 mA (MAX.) at TA = 25°C ■ HIGH NOISE IMMUNITY V n i H = V n il = 28% Vcc (MIN.) 1 1 B1N

circuit diagram of MOD 100 counter using ic 7490

Abstract: RSC14 plcf circuit diagram of MOD 8 counter using ic 7490 R14C11
Contextual Info: Data Sheet June 1999 m i c r o e l e c t r o n i c s group Lucent Technologies Bell Labs Innovations ORCA Series 3C and 3T Field-Programmable Gate Arrays Features • High-performance, cost-effective, 0.35 pm OR3C and 0.3 pm (OR3T) 4-level metal technology, (4- or 5-input

TFC 718 S

Abstract: kss 213 c sony sony KSS 213 b sony KSS 123 sony KSS 121
Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order this document by: DSP56007/D DSP56007 SYMPHONY AUDIO DSP FAMILY 24-BIT DIGITAL SIGNAL PROCESSORS Motorola designed the Symphony™ family of high-performance, programm able Digital Signal Processors DSPs to support a variety of digital audio applications, including Dolby ProLogic,

UPD482445GW-70

Abstract: UPD482445
Contextual Info: DATA SHEET MOS INTEGRATED CIRCUIT UPD482444, 482445 4M-Bit Dual Port Graphics Buffer 256K-WORD BY 16-BIT D es crip tio n The ,uPD482444 and ,uPD482445 have a random access port and a serial access port. The random access port has a 4M-bit 262, 144 words x 16 bits memory cell array structure. The serial access port can perform clock

NEC uPD 688

Abstract: UPD4217400LG3-A60
Contextual Info: DATA SHEET NEC / MOS INTEGRATED CIRCUIT / //PD42S16400L, 4216400L, 42S17400L, 4217400L 3.3 V OPERATION 16 M-BIT DYNAMIC RAM 4 M-WORD BY 4-BIT, FAST PAGE MODE Description The ¿/PD42S16400L, 4216400L, 42S17400L, 4217400L are 4,194,304 words by 4 bits CMOS dynamic RAMs, The

Contextual Info: DATA SHEET NEC / MOS INTEGRATED CIRCUIT _ ¿ ¿ P D 4 2 1 8 0 5 1 M-BIT DYNAMIC RAM 128K-WORD BY 8-BIT, HYPER PAGE MODE EDO Description The /iPD421805 is a 131,072 words by 8 bits CMOS dynamic RAM with optional hyper page mode (EDO).