XXXXXA Search Results

M41T00S

Abstract: ds1340 ISL12008
Contextual Info: Replacing the M41T00S and DS1340 RTC with the ISL12008 Technical Brief December 15, 2008 Introduction TB479.0 • Alarm 5 register address bits are “don’t care” bits XXXXXA2A1A0 . For example, register address 09h (00001001b) is same as 01h (00000001b), or 1Ah

FiTel DFB Laser

Abstract: automatic DFB laser power control FRL15TCWx FRL15TCW FRL15TCWx-D86-xxxxx tunable laser diode Tunable Optical Filter 50 GHz FRL15TCWA FiTel photodiode
Contextual Info: Data Sheet FRL15TCWx-D86-xxxxxA Mar. 2011 Full Band Tunable DFB Laser Module Applications  Long Haul or Metropolitan DWDM Transmission Systems  Dynamic Wavelength Provisioning and Add/Drop Multiplexer Descriptions  FRL15TCWx-D86 series is full band tunable DFB laser module designed for long haul

Contextual Info: SM/SMJ34061 VIDEO SYSTEM CONTROLLER JULY 1 98 7 • Generates User-Programmable Control Signals Horizontal Sync, Vertical Sync, and Blanking Which Support a Broad Range of Raster-Scan Display Systems with Varying Resolutions and Scan Rates S M J 3 4 0 6 1 G B . . . 68-P IN PGA

TS PQ4 12

Abstract: TS PQ4 24 ts pq4 10 TS PQ4 20 TS PQ4 120
Contextual Info: in y 1.0 80960HA/HD/HT About This Document This document describes the parametric performance of Intel’s 80960Hx embedded superscalar microprocessors. Detailed descriptions for functional topics — other than parametric performance — are published in the i960 H x M icroprocessor U ser’s Guide 272484 .

Contextual Info: HM5118160BI Series 1048576-word x 16-bit Dynamic Random Access Memory HITACHI ADE-203-580A Z Rev. 1.0 May. 20, 1996 Description The Hitachi HM5118160BI is a CMOS dynamic RAM organized as 1,048,576-word x 16-bit. It employs the most advanced CMOS technology for high performance and low power. The HM5118160BI offers

Contextual Info: . MMMtekaatr', _*-V 4* ." •Y >*'V WffffrtHHHIIIIttllMtv^ . ■i ¿Mtf .v^-vj CY7C09269/79/89 CY7C09369/79/89 P R E L IM IN A R Y 16K/32K/64K x16/18 Synchronous Dual Port Static RAM • Low operating power Features • True Dual-Ported memory cells which allow simulta­

Contextual Info: CY7C09269V/79V/89V CY7C09369V/79V/89V PRELIMINARY 3.3V 16K/32K/64Kx 16/18 Synchronous Dual-Port Static RAM Features • True Dual-Ported memory cells which allow simulta­ neous access of the same memory location • 6 Flow-Through/Pipelined devices — 16K x 16/18 organization CY7C09269V/369V

Contextual Info: DATA SHEET MOS INTEGRATED CIRCUIT 1M-BIT CMOS SYNCHRONOUS FAST SRAM 32K-WORD BY 36-BIT PIPELINED OPERATION Description The ,uPD431636L is a 32,768-word by 36-bit synchronous static RAM fabricated with advanced CMOS technology using N-channel four-transistor memory cell.

power switch transistor dk51

Abstract: DK51 transistor transistor dk51 Yamaha YOP-1 DDR B61 hall yamaha b-60 SERVICE MANUAL AGS3 cde tsc ADSP-2180 Yamaha AX 496
Contextual Info: ADSP-219x/2192 DSP Hardware Reference Revision 1.1, April 2004 Part Number 82-002001-01 Analog Devices, Inc. One Technology Way Norwood, Mass. 02062-9106 a Copyright Information 2004 Analog Devices, Inc., ALL RIGHTS RESERVED. This document may not be reproduced in any form without prior, express written consent

mr4040

Abstract: sma e1017 BT 2323 AUDIO CONTROLLER PIN DETAILS ADSP-2199x dc geared motor 60 rmp ADSP-2100 ADSP-21992 summit-ICE ASY 48 VI IC tda 2151
Contextual Info: Preliminary ADSP-2199x Mixed Signal DSP Controller Hardware Reference Preliminary Revision 0, 2003 Part Number: 82-000640-01 Analog Devices, Inc. Digital Signal Processor Division One Technology Way Norwood, Mass. 02062-9106 Preliminary Copyright Information

Contextual Info: fax id: 5209 CY7C09349V CY7C09359V :/ C Y P R E S S 3.3V 4K/8K x 18 Synchronous Dual-Port Static RAM • High-speed clock to data access 7.5/12 ns max. • 3.3V Low operating power Features • True Dual-Ported m em ory cells which allow simulta­ neous access of the same memory location

Contextual Info: CY7C09079/89/99 CY7C09179/89/99 PRELIMINARY 32K/64K/128K x 8/9 Synchronous Dual-Port Static RAM • High-speed clock to data access 6.5/7.5/9/12 ns max. Features • Low operating power • True Dual-Ported memory cells which allow simulta­ neous access of the same memory location

560 ohm RESISTOR

Abstract: B12-B1 68-PIN SMJ34061GB
Contextual Info: S M /S M J 3 4 0 6 1 VIDEO SYSTEM CONTROLLER JULY 1 9 8 7 • S M J 3 4 0 6 1 G B . . . 68-P IN PGA CERAM IC PA CK AG E* Generates User-Programmable Control Signals Horizontal Sync, Vertical Sync, and Blanking W hich Support a Broad Range of Raster-Scan Display Systems w ith Varying

F0411

Abstract: i87C51FB LQ 425 B8 LQ 425 B7 TQFP Package 44 lead 87c51 i87C51 P89CE558 PLCC-44 SST89C54 SST89C58
Contextual Info: FlashFlex51 MCU SST89C54 / SST89C58 / SST89C59 Advance Information FEATURES: • • Multi-Purpose 8-bit 8051 Family Compatible M icrocontroller Unit MCU with Embedded SuperFlash Memory for Flexibility Fully Software and Development Toolset Compatible as well as Pin-For-Pin Package

ar305

Abstract: MPC555 QADC64 AR212 AR231 AR304 bbc 598
Contextual Info: TRANSPORTATION SYSTEMS GROUP CUSTOMER ERRATA AND INFORMATION SHEET Part: MPC555.C General Business Use Report Generated: Tue Dec 10, 2002, 16:11:32 Page 1 = | MPC555.C | =

MIC710

Abstract: XC6875 MC1741L C4558C SG425 mc7724c NE533V General Instrument data book 741p SN75107
Contextual Info: Master Index and Cross Reference Guide M IL-M -38510 Program and Chip Information Operational Amplifiers Voltage Regulators Interface Circuits Voltage Comparators Consumer Circuits Other Linear Circuits Package Information and Mounting Hardware Application Notes

SVC 561-10

Abstract: AXP 192 AXP 223 000D 161A-2 161A3 FBRX
Contextual Info: Alpha AXP Architecture Handbook Order Number EC–QD2KA–TE Revision/Update Information: Digital Equipment Corporation Maynard, Massachusetts This is Version 2 of the Alpha AXP Architecture Handbook. October 1994 While Digital believes the information included in this publication is correct as of the date of publication,

hilti te 24

Abstract: hilti te 17 GO 440 104 esm 433 rac
Contextual Info: DATA SHEET NEC MOS INTEGRATED CIRCUIT ¿¿P D 42S18165L , 4 2 1 8 1 6 5 L 3.3 V OPERATION 16 M-BIT DYNAMIC RAM 1 M-WORD BY 16-BIT, EDO, BYTE READ/WRITE MODE Description The .¿/PD42S18165L, 4218165L are 1,048,576 words by 16 bits CMOS dynamic RAMs with optional EOO

Contextual Info: PRELIMINARY DATA SHEET NEC MOS INTEGRATED CIRCUIT ¿ ¿ P D 4 2 6 4 16 0 , 4 2 6 5 16 0 64 M-BIT DYNAMIC RAM 4M -W O RD BY 16-BIT, FAST PAGE MODE Description The /iP D 426 416 0,4265160 are 4,194,304 words by 16 bits dynamic C MOS RAMs. The fast page mode capability

Contextual Info: Preliminary a Advanced Micro Devices Am79C864 Physical Layer Controller PLC DISTINCTIVE CHARACTERISTICS Implements FDDI PHY layer protocol for ISO standard (FDDI) 9314-1 • ■ Repeat Filter ■ Hardware Physical Connection Management (PCM) support ■

D-SUB FOR VGA Amphenol

Abstract: 15P D-SUB analog RGB from DVI input to RGB output VGA iec 60945 HATTELAND TRANSISTOR c 5578 B VSD100692-3 VSD100692-4 EN60945 vga cutout dimensions
Contextual Info: DATA SHEET Manufacturer: Hatteland Display AS Product: 26.0 inch Maritime Multi Display MMD Type: JH 26T11 MMD-xxx-Axxx Last Revised: Revision#: 27 May 2011 13 26.0 inch Widescreen (MMD) - Series 1 Features: This Series 1 widescreen is by factory default optically bonded which ensures that the

Contextual Info: HIGH-SPEED 16Kx 16 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM PRELIMINARY IDT709269S/L Integrated Device Technology, Inc. FEATURES: • • True Dual-Ported m em ory cells w hich allow sim ulta­ neous access of the sam e m em ory location • H igh-speed clock to data access

3 DG 1008

Abstract: MRF 530 PEWI CY7C451 CY7C453
Contextual Info: n r CYPRESS • • • • • • • • • • • • • 512 x 9 Cascadable Clocked and 2K x 9 Cascadable Clocked FIFOs with Programmable Flags Functional D escription Features • CY7C451 CY7C453 512 x 9 CY7C4S1 an d 2,048 x 9 (CY7C453) FIFO buffer m em ory

AXP 223

Abstract: 000D 21068 EV45 21164a Alpha 21164PC
Contextual Info: Alpha Architecture Handbook Order Number EC–QD2KB–TE Revision/Update Information: This is Version 3 of the Alpha Architecture Handbook. The changes and additions in this book are subsequent to the Alpha AXP Architecture Reference Manual, Second Edition, and the Alpha AXP Architecture Handbook, Version 2.