XC2V1000 COMPLETE Search Results

XC2V1000 COMPLETE Result Highlights (4)

Part	ECAD Model	Manufacturer	Description	Download	Buy
ADS1293CISQX/NOPB		Texas Instruments	Complete Low-Power Integrated Analog Front End for ECG Applications 28-WQFN -20 to 85
LM3533TME-40/NOPB		Texas Instruments	Complete lighting solution for smartphone handsets 20-DSBGA -40 to 125
LM3533TMX-40/NOPB		Texas Instruments	Complete lighting solution for smartphone handsets 20-DSBGA -40 to 125
ADS1293CISQE/NOPB		Texas Instruments	Complete Low-Power Integrated Analog Front End for ECG Applications 28-WQFN -20 to 85

XC2V1000 COMPLETE Datasheets Context Search

Catalog Datasheet	Type	Document Tags	PDF
XC2V1000 Abstract: XC2V1000 complete datasheet FF1152 DS031-4 v3.4 AF124 XC2V3000 Contextual Info: 1 Virtex-II Platform FPGAs: Complete Data Sheet R DS031 v3.4 March 1, 2005 Product Specification Module 1: Introduction and Overview Module 3: DC and Switching Characteristics 7 pages 43 pages • • • • • • • • • • • • Summary of Features	Original	DS031 18-Kb 18-Bit DS031-4 XC2V1000 XC2V1000 complete datasheet FF1152 DS031-4 v3.4 AF124 XC2V3000	PDF
XC2V1500 Abstract: FG256 FG676 BG728 CS144 AL205 LVDCI25 661129 j337 wireless encrypt Contextual Info: Virtex-II Platform FPGAs: Complete Data Sheet R DS031 March 29, 2004 Product Specification This document includes all four modules of the Virtex-II Platform FPGA data sheet. Module 1: Introduction and Overview Module 3: DC and Switching Characteristics	Original	DS031 DS031-1 DS031-3 DS031-2 FF1152) BF957) DS031-4 XC2V1500 FG256 FG676 BG728 CS144 AL205 LVDCI25 661129 j337 wireless encrypt	PDF
digital FIR Filter verilog code Abstract: XC2V6000 XC2V1000 XC2V1500 XC2V2000 XC2V250 XC2V40 XC2V500 XC2V80 K217 Contextual Info: Virtex -II Platform FPGAs: Introduction and Overview R DS031-1 v1.9 September 26, 2002 Advance Product Specification Summary of Virtex-II Features • Industry First Platform FPGA Solution • IP-Immersion Architecture - Densities from 40K to 8M system gates	Original	DS031-1 18-bit DS031-4 digital FIR Filter verilog code XC2V6000 XC2V1000 XC2V1500 XC2V2000 XC2V250 XC2V40 XC2V500 XC2V80 K217	PDF
XC2V1500 Abstract: XC2V80 XC2V1000 XC2V2000 XC2V250 XC2V40 XC2V500 lightning event counter AF124 XC2V4000 Contextual Info: Virtex -II Platform FPGAs: Introduction and Overview R DS031-1 v1.9 September 26, 2002 Advance Product Specification Summary of Virtex-II Features • Industry First Platform FPGA Solution • IP-Immersion Architecture - Densities from 40K to 8M system gates	Original	DS031-1 18-bit 18-bit BG728 DS031-4 XC2V1500 XC2V80 XC2V1000 XC2V2000 XC2V250 XC2V40 XC2V500 lightning event counter AF124 XC2V4000	PDF
ra1613 Abstract: FB360 HSTL18 XC2V3000-BG728 XC3S1000-FT256 XC3S200-ft256 X2P376 X2P528 X2P680 BGA 728 35x35 1.27 Contextual Info: XPressArray-II 0.15mm Structured ASIC Data Sheet 1.0 Key Features • Next-generation 0.15mm hybrid structured ASIC • Initializable distributed memory at speeds up to 210MHz • Platform for high-performance 1.5V/1.2V ASICs and FPGAto-ASIC conversions • Configurable signal, core and I/O power supply pin locations	Original	210MHz PCI33, PCI66, ra1613 FB360 HSTL18 XC2V3000-BG728 XC3S1000-FT256 XC3S200-ft256 X2P376 X2P528 X2P680 BGA 728 35x35 1.27	PDF
XC2V1000 Pin-out Abstract: Virtex-II Field-Programmable Gate Arrays XC2V80 IEEE1532 XC2V1000 XC2V1500 XC2V250 XC2V40 XC2V500 Contextual Info: Virtex-II 1.5V Field-Programmable Gate Arrays R DS031-1 v1.7 October 2, 2001 Advance Product Specification Summary of Virtex -II Features • Industry First Platform FPGA Solution • IP-Immersion Architecture - Densities from 40K to 8M system gates	Original	DS031-1 18-Kbit 18-bit DS031-1, DS031-2, DS031-3, DS031-4, XC2V1000 Pin-out Virtex-II Field-Programmable Gate Arrays XC2V80 IEEE1532 XC2V1000 XC2V1500 XC2V250 XC2V40 XC2V500	PDF
microblaze ethernet Abstract: microblaze XC2V1000 XC2V1000-4FG456C virtex memec xilinx vhdl rs232 code vhdl code for rs232 XC2V1000 XC2V1000 complete lcd module verilog architecture in 4289 Contextual Info: VirtexII Microblazebb 3/21/02 12:47 PM Page 1 Virtex-II MicroBlaze Development Kit TM TM Product Brief The Virtex-II MicroBlaze Development Kit is a quick, flexible and feature rich prototype platform. Features • Easy to use modular development platform	Original	16-bit microblaze ethernet microblaze XC2V1000 XC2V1000-4FG456C virtex memec xilinx vhdl rs232 code vhdl code for rs232 XC2V1000 XC2V1000 complete lcd module verilog architecture in 4289	PDF
XC4VLX25-11FF668I Abstract: XC4VSX35-10FF668C XC4VSX35-10FFG668I XC4VLX25-10FF668C XC2VP20-5FF896C XC4VLX40-10FF668I XC4VLX25-10FF668I XC4VSX35-11FF668I XC2VP30-7FF896C XC4VSX25 Contextual Info: Additional Source for Thermal Adhesive in Certain Flip-Chip Packages for Virtex-II, Virtex-II Pro, and Virtex-4 FYI−For Your Information XCN06012 v1.0 May 1, 2006 Overview This notice describes the qualification of a second source thermal adhesive and lid attach adhesive material for flip-chip	Original	XCN06012 XC2VP70-5FF1517I XC2VP70-7FF1517C XC2VP70-6FFG1517C XC2VPX20-5FF896C XC2VP70-5FF1704I XC2VP70-7FF1704C XC2VP70-6FFG1517I XC2VPX20-6FF896C XC2VP70-6FF1517C XC4VLX25-11FF668I XC4VSX35-10FF668C XC4VSX35-10FFG668I XC4VLX25-10FF668C XC2VP20-5FF896C XC4VLX40-10FF668I XC4VLX25-10FF668I XC4VSX35-11FF668I XC2VP30-7FF896C XC4VSX25	PDF
LVDSEXT-25 Abstract: 16x1D LVPECL33 16X1S LVDS-25 LVDS-33 LVDSEXT25 LVDCI18 LVDCI25 LVDS25 Contextual Info: Virtex-II 1.5V Field-Programmable Gate Arrays R DS031-2 v1.9 November 29, 2001 Advance Product Specification Detailed Description Input/Output Blocks (IOBs) Table 1: Supported Single-Ended I/O Standards Virtex-II I/O blocks (IOBs) are provided in groups of two or	Original	DS031-2 LVCMOS33 LVCMOS25 DS031-1, DS031-3, DS031-4, DS031-2, LVDSEXT-25 16x1D LVPECL33 16X1S LVDS-25 LVDS-33 LVDSEXT25 LVDCI18 LVDCI25 LVDS25	PDF
3S1000FG456-4C Abstract: PCI64 vhdl code for 8 bit parity generator vhdl code for parity checker 2-S200 Contextual Info: LogiCORE PCI64 Interface v3.0 DS205 April 14, 2003 Introduction LogiCORE Facts With the Xilinx LogiCORE PCI Interface, a designer can build a customized PCI 2.3-compliant core with the highest possible sustained performance, 528 Mbytes/sec. Features •	Original	PCI64 DS205 64-bit, 32-bit 64/32-bit PCI64/33 3S1000FG456-4C vhdl code for 8 bit parity generator vhdl code for parity checker 2-S200	PDF
spartan 3a Abstract: SPARTAN-3 XC3S400 24v 12v 20A regulator circuit diagram power supply SAMSUNG MONITOR str panasonic 614 battery 10nF 50V X7R samsung 7 pin str for 24v 3 amp to 220 package Circuit diagram of Regulated Power supply 6V 5A EL7566 ISL6401 Contextual Info: HIGH PERFORMANCE ANALOG Power Management Application Guide for Xilinx FPGAs Using Switchers to Power Xilinx FPGAs and DDR Memory Increased gate counts and higher clock speeds in programmable logic ICs have resulted in higher current requirements while smaller device geometries are driving lower core supply voltages. Both	Original		PDF
SPARTAN-3 XC3S400 Abstract: SPARTAN-II xc2s200 SPARTAN-3 XC3S1000 20-tssop atmel 032 xcv400 bi directional buffer on the I/O pin AT17 AT40KAL XC2V80 XCV100E Contextual Info: Features • Very Low-cost Configuration Memory • Programmable 1,048,576 x 1, 2,097,152 x 1, 4,194,304 x 1 and 7,340,032 x 1-bit Serial • • • • • • • • • • • • • • • Memories Designed to Store Configuration Programs for Field Programmable Gate	Original		PDF
XC17V00 Abstract: xilinx SO20 MARKING CODE PC44 SO20 VQ44 SelectMAP Contextual Info: R DS073 v1.11 June 7, 2007 XC17V00 Series Configuration PROMs Product Specification 8 Features • Available in compact plastic packages: VQ44, PC44, PC20, VO8, and SO20 • Programming support by leading programmer manufacturers. Cascadable for storing longer or multiple bitstreams	Original	DS073 XC17V00 XC3S50 XC17V04, XC17V02, XC17V01, XC17V16 XC17V08, xilinx SO20 MARKING CODE PC44 SO20 VQ44 SelectMAP	PDF
XC2V1000FG256-4 Abstract: XAPP639 XC2V1000 XC2V3000 flood v10 crc verilog code 16 bit XC2V1000-FG256 Contextual Info: Application Note: Virtex-II Family R HyperTransport Lite Interface for Virtex-II FPGAs XAPP639 v1.0 January 7, 2003 Summary HyperTransport is a high-speed bus designed to move data from processors to peripherals at speeds up to 60 times faster than a 32-bit PCI bus operating at 66 MHz. The HyperTransport	Original	XAPP639 32-bit XAPP639 XC2V1000 XC2V1000FG256-4 XC2V3000 flood v10 crc verilog code 16 bit XC2V1000-FG256	PDF

spartan 3a Abstract: 48-pin TSOP Package VO48 XCF02S RELIABILITY REPORT xcf128x XCF32PFS48C Virtex 4 XC4VFX60 XC3S400 XCF02S pcb XCF32P Device Reliability report XILINX Contextual Info: 48 Platform Flash In-System Programmable Configuration PROMs R DS123 v2.15 July 07, 2008 Product Specification Features • In-System Programmable PROMs for Configuration of Xilinx FPGAs • ♦ 3.3V Supply Voltage Low-Power Advanced CMOS NOR Flash Process	Original	DS123 VOG20 spartan 3a 48-pin TSOP Package VO48 XCF02S RELIABILITY REPORT xcf128x XCF32PFS48C Virtex 4 XC4VFX60 XC3S400 XCF02S pcb XCF32P Device Reliability report XILINX	PDF
UG161 Abstract: XCF128X COOLRUNNER-II example led xc6slx75t XC3SD3400A xc5vlx220t XCF02S RELIABILITY REPORT virtex 6 XC6VSX475T xc6slx75 XC6VLX365T Contextual Info: Platform Flash PROM User Guide UG161 v1.5 October 26, 2009 R R Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit the	Original	UG161 XAPP694, XAPP544, XCF02S/XCF04S XAPP389, UG002, UG071, UG191, UG332, UG360, UG161 XCF128X COOLRUNNER-II example led xc6slx75t XC3SD3400A xc5vlx220t XCF02S RELIABILITY REPORT virtex 6 XC6VSX475T xc6slx75 XC6VLX365T	PDF
qfn 3x3 tray dimension Abstract: XCDAISY BFG95 XC5VLX330T-1FF1738I pcb footprint FS48, and FSG48 WS609 jedec so8 Wire bond gap XC3S400AN-4FG400I FFG676 XC4VLX25 cmos 668 fcbga Contextual Info: Device Package User Guide [Guide Subtitle] [optional] UG112 v3.5 November 6, 2009 [optional] R R Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit the	Original	UG112 UG072, UG075, XAPP427, qfn 3x3 tray dimension XCDAISY BFG95 XC5VLX330T-1FF1738I pcb footprint FS48, and FSG48 WS609 jedec so8 Wire bond gap XC3S400AN-4FG400I FFG676 XC4VLX25 cmos 668 fcbga	PDF