X851 Search Results

CNT04RE

Abstract: XC4000E
Contextual Info: Symmetric, 16-Deep Time Skew Buffer March 16, 1998 Product Specification R Xilinx Inc. 2100 Logic Drive San Jose, CA 95124 Phone: +1 408-559-7778 Fax: +1 408-559-7114 E-mail: coregen@xilinx.com URL: www.xilinx.com data is registered and presented on the Q pins of the

cascading diode

Abstract: XC4000E
Contextual Info: dsp_pdafir.fm Page 59 Friday, March 20, 1998 4:21 PM Parallel Distributed Arithmetic FIR Filter March 23, 1998 Product Specification R Xilinx Inc. 2100 Logic Drive San Jose, CA 95124 Phone: +1 408-559-7778 Fax: +1 408-559-7114 E-mail: coregen@xilinx.com URL:

precision Sine Wave Generator

Abstract: XC4000 XC4000E sine cosine function generator pt 116
Contextual Info: dsp_trigtabl.fm Page 75 Monday, July 6, 1998 5:52 PM Sine/Cosine July 17, 1998 Product Specification R Xilinx Inc. 2100 Logic Drive San Jose, CA 95124 Phone: +1 408-559-7778 Fax: +1 408-559-7114 E-mail: coregen@xilinx.com URL: www.xilinx.com format. However, values for theta may be provided in either

XC4000E

Abstract: 3 taps filters
Contextual Info: Parallel Distributed Arithmetic FIR Filter December 30, 1998 Product Specification R Xilinx Inc. 2100 Logic Drive San Jose, CA 95124 Phone: +1 408-559-7778 Fax: +1 408-559-7114 E-mail: coregen@xilinx.com URL: www.xilinx.com Features • • • • • •

circuit diagram electronic choke for tube light

Abstract: 40w ELECTRONIC choke BALLAST DIAGRAM m861 ELECTRONIC BALLAST DIAGRAM 400W circuit diagram electronic ballast for 40W tube l U804 TUBE Light Choke function 2 way lighting circuit 40w electronic ballast circuit diagram dimmer 230V circuit diagram
Contextual Info: MEMSTYLE SPECTRA Modules range TECHNICAL INFORMATION SPECTRA Modules range Coverplate, Grid and Mounting Box Selection Guide GANG 1 2 3 4 6 8 9 12 18 24 M803 M804 M806 M808 U803 U804 U806 STAINLESS STEEL/MATT CHROME A801SS A802SS A803SS A804SS SATIN BRONZE

Contextual Info: X Kontaktanordnung Contact arrangement 31 27 29 23 25 19 21 15 17 11 13 64 S i g n a l 6k s i g n a l Kontakte contacts z 7 9 2:1 bi = K o n t a k t p o s i t i o n b e l e g t = p o s it io n vith contact — a — c 1 0 ,6 . 0 , 2 □ = Kontaktposition nicht belegt

Contextual Info: x Kontaktanordnung Contact 31 27 29 23 19 21 25 96 arrangement 15 17 11 13 Signal Kontakte 96 s l g n a l contacts z 2:1 7 9 bi = K o n t a k t p o s i t i o n = posltIon vlth belegt contact — a — c □ = Kontaktposition = positlon vlthout nicht 1 0 , 6 . 0,2

Contextual Info: X Kontaktanordnung A 96 S i g n a l con ta ct arrangement Kontakte 96 s i g n a l c o n t a c t s 31 27 29 23 25 19 15 17 21 11 13 z 2:1 7 9 bi — a — c = Kontaktposition belegt - p o s i t i o n with con ta ct 1 0 ,6 □ = Kontaktposition nicht belegt

FTLX85

Abstract: 8512D3B AN-2038 2000MHz transceiver 10G optical laser FTLX8512D3BCL
Contextual Info: Finisar Productt Specificaation RoHS-6 Complliant 10G Gb/s 850 0nm Multtimode Datacom D XFP Optical Traansceiverr FTLX8 8512D3B BCL PRO ODUCT FEA ATURES • Hot-plugg gable XFP fo ootprint • Supports 8.5Gb/s to 10.5Gb/s* 1 bit rates • Power disssipation <1.5W

CNT04RE

Abstract: XC4000E
Contextual Info: dsp_tsb16s.fm Page 85 Tuesday, July 14, 1998 7:45 AM Symmetric, 16-Deep Time Skew Buffer July 17, 1998 Product Specification R Xilinx Inc. 2100 Logic Drive San Jose, CA 95124 Phone: +1 408-559-7778 Fax: +1 408-559-7114 E-mail: coregen@xilinx.com URL: www.xilinx.com

Contextual Info: 2 4 3 5 X Kontaktanordnung cont act arrangement 32 I 30 28 I 26 24 I 22 18 20 16 I I U 12 I 10 6 2 _ z k 8 Einpress - Kontakte 48 p r e s s - i n - cont act s Position position 2: 1 15,6 a— e— 7 6 = Kontaktpos i t i on bel egt = p o s i t i o n wi t h cont act

digital FIR Filter using distributed arithmetic

Abstract: cascading diode spartan 3 fir filter FIR FILTER xilinx
Contextual Info: dsp_pdafir.fm Page 59 Tuesday, July 14, 1998 7:49 AM Parallel Distributed Arithmetic FIR Filter July 17, 1998 Product Specification R Xilinx Inc. 2100 Logic Drive San Jose, CA 95124 Phone: +1 408-559-7778 Fax: +1 408-559-7114 E-mail: coregen@xilinx.com URL:

FTLX85

Abstract: FTLX8512D3B
Contextual Info: Finisar Producct Specificaation Indu ustrial Teemperatu ure Rangge 10G Gb/s 850 0nm Multtimode Datacom D XFP Optical Traansceiverr X8512D3B BTL PRO ODUCT FEA ATURES • Hot-plugg gable XFP fo ootprint • Supports 8.5Gb/s to 10.5Gb/s 1 bit rates* • Power disssipation <1.5W

precision Sine Wave Generator

Abstract: sine cosine function generator XC4000 XC4000E X8140
Contextual Info: dsp_trigtabl.fm Page 75 Wednesday, March 4, 1998 3:36 PM Sine/Cosine March 16, 1998 Product Specification R Xilinx Inc. 2100 Logic Drive San Jose, CA 95124 Phone: +1 408-559-7778 Fax: +1 408-559-7114 E-mail: coregen@xilinx.com URL: www.xilinx.com format. However, values for theta may be provided in either

XAPP851

Abstract: ddr phy VIRTEX-5 DDR PHY ddr phy design DDR400 JESD79E PC3200 sdram pcb layout ddr IDELAY x851
Contextual Info: Application Note: Virtex-5 Family DDR SDRAM Controller Using Virtex-5 FPGA Devices R Author: Toshihiko Moriyama and Rich Chiu XAPP851 v1.1 July 14, 2006 Summary This application note describes a 200-MHz DDR SDRAM (JEDEC DDR400, PC3200 standard) controller implemented in a Virtex -5 device. This implementation uses IDELAY elements to