X3491 Search Results

Contextual Info: flX IU N XC7336 36-Macrocell CMOS EPLD X Preliminary Product Specifications Features General Description • The XC7336 is a member of the Xilinx Dual-Block EPLD family. It consists of four Fast Function Blocks intercon­ nected by a central Universal Interconnect Matrix UIM .

Contextual Info: XC7354 54-Macrocell CMOS EPLD Product Specifications Features The Universal Interconnect Matrix connects the Function Blocks to each other and to all input pins, providing 100% connectivity between the Function Blocks. This allows logic functions to be mapped into the Function Blocks and

MC3 117

Abstract: MC128 XC73108 mc103 10 pin MC124 MC116 MC92 mc11-6 PC84 PQ160
Contextual Info:  XC73108 108-Macrocell CMOS CPLD June 1, 1996 Version 1.0 Product Specification Features Macrocells can individually be specified for high performance or low power operation by adding attributes to the logic schematic, or declaration statements to the behavioral

AX209

Abstract: IEC-801-2 ESD MAX485 rx tx MAX244 AX232 MAX237 "direct replacement" rs232 mouse ax211
Contextual Info: LINE DRIVERS/RECEIVERS | AppleTalk RS •232 see next page for RS-485/RS-422 MAX216 1 single-ended driver/2-single-ended receivers, 1 differential driver/1 differential receiver +3V POWERED - - 4 DRVRS, 5 RCVRS +5V, 4 EXT. CAPS +5V. INTERNAL CAPS - — 2 DRVRS, 2 RCVRS

Contextual Info: E xilin x XC7354 54-Macrocell CMOS CPLD June 1, 1996 Version 1.0 Product Specification Features O perating current for each design can be approxim ated for specific operating conditions using the following equation: • • • • • • • • • •

Contextual Info: £ X IL IN X XC7354 54-Macrocell CMOS EPLD Preliminary Product Specifications Features • High-Performance EPLD - 10 ns pin-to-pin delay - 100 MHz maximum clock frequency • Advanced Dual-Block architecture - Two Fast Function Blocks - Four High-Density Function Blocks

X3483

Abstract: MAX3491 ic max3485
Contextual Info: 19-03 3 3 ; R e v 0; 12/94 3 .3 V -P o w e r e d , 1 0 M b p s a n d S le w -R a te -L im ite d t r u e R S -4 8 5 /R S -4 2 2 T r a n s c e iv e rs Drivers are short-circuit current limited and are protect­ ed a g a in s t e x c e s s iv e p o w e r d is s ip a tio n by th e rm a l

A7 SMD TRANSISTOR

Abstract: fnd 503 7-segment 4013 FLIP FLOP APPLICATION DIAGRAMS SMD fuse P110 HP 1003 WA transistor SMD making code GC 1736DPC verilog code for 32 BIT ALU implementation xilinx xc95108 jtag cable Schematic RCL TOKO data
Contextual Info: Data Book The Programmable Logic Data Book Success made simple Click anywhere on this page to continue 9/96 On behalf of the employees of Xilinx, our sales representatives, our distributors, and our manufacturing partners, welcome to our 1996 Data Book, and thank you for your interest in

apple ipad 2 circuit schematic

Abstract: SMD TRANSISTOR MARKING P28 fnd 503 7-segment apple ipad schematic drawing smd code marking NEC tantalum capacitor marking w25 SMD 32 pin eprom to eprom copier circuit pin DIAGRAM OF IC 7400 smd TRANSISTOR code marking bu TRANSISTOR SMD MARKING CODE W25
Contextual Info: Data Book The Programmable Logic Data Book Success made simple Click anywhere on this page to continue 1996 On behalf of the employees of Xilinx, our sales representatives, our distributors, and our manufacturing partners, welcome to our 1996 Data Book, and thank you for your interest in

Contextual Info: £X IU N X XC7354 54-Macrocell CMOS CPLD June 1,1996 Version 1.0 Product Specification Features Operating current for each design can be approximated for specific operating conditions using the following equation: • • • • • • • • • •

Contextual Info: XC73108 108-Macrocell CMOS EPLD Product Specifications Features • H ig h -P erfo rm an c e E P L D - 7 .5 ns pin-to-pin s p e e d on all fast inputs - 125 M H z m axim um clock freq uen cy • A dvanced D ual-B lock architecture - 2 F ast Function Blocks

Contextual Info: £XILIN X XC73108 108-Macrocell CMOS CPLD June 1, 1996 Version 1.0 Product Specification Features Macrocells can individually be specified for high perfor­ mance or low power operation by adding attributes to the logic schematic, or declaration statements to the behavioral

Contextual Info: H XC73144 144-Macrocell CMOS EPLD M U N ÎT Product Specifications Features • High-Performance EPLD - 7.5 ns pin-to-pin speed on all fast inputs - 100 MHz maximum clock frequency • Advanced Dual-Block architecture - Four Fast Function Blocks - Twelve High-Density Function Blocks

XC7372

Contextual Info: HXILINX XC7372 72-Macrocell CMOS CPLD June 1 ,1 9 9 6 Version 1.0 Product Specification Features tion Blocks are turned off and unused m acrocells in used Function Blocks are configured for low power operation. • High-perform ance Com plex Program mable Logic

Contextual Info: £ XC7372 72-Macrocell CMOS EPLD x ilin x Product Specifications Features connectivity between the Function Blocks. This allows logic functions to be mapped into the Function Blocks and interconnected without routing restrictions. • High-Performance EPLD

Contextual Info: flX I L I N X XC73108 108-Macrocell CMOS CPLD June 1,1996 Version 1.0 Product Specification Features Macrocells can Individually be specified for high perfor­ mance or low power operation by adding attributes to the logic schematic, or declaration statements to the behavioral

Contextual Info: K XC73144 144-Macrocell CMOS CPLD x il in x June 1,1996 Version 1.0 Product Specification Features description. To minimize power dissipation, unused Func­ tion Blocks are turned off and unused macrocells in used Function Blocks are configured for low power operation.

MC5246

Abstract: MC-5246 J15H
Contextual Info: flXILINX 108-Macrocell CMOS CPLD January, 1997 Version 1.0 Product Specification Features M acrocells can individually be specified for high perfor­ mance or low power operation by adding attributes to the logic schematic, or declaration statem ents to the behavioral

MC25

Abstract: mc161 R1542
Contextual Info: f lX IU N X XC73144 144-Macrocell CMOS CPLD January, 1997 Version 1.0 Product Specification Features tion Blocks are turned off and unused macrocells in used Function Blocks are configured for low power operation. • • • • • • • • • •

XC7354

Contextual Info: flXIUNX XC7354 54-Macrocell CMOS CPLD June 1, 1996 Version 1.0 Product Specification Features Operating current for each design can be approximated for specific operating conditions using the following equation: • • • • • • • • • • •

MC66 20 pin circuit

Abstract: MC67 XC7354-15 XC7354-10 MC65 20 pin circuit PC44 XC7354 X3491
Contextual Info:  XC7354 54-Macrocell CMOS CPLD June 1, 1996 Version 1.0 Product Specification Features Operating current for each design can be approximated for specific operating conditions using the following equation: • • • • • • • • • • • •

XC7372

Contextual Info: £ XC7372 72-Macrocell CMOS EPLD XILINX Product Specifications connectivity between the Function Blocks. This allows logic functions to be mapped into the Function Blocks and interconnected without routing restrictions. Features • • H ig h -P erfo rm an c e E P L D

mc16

Abstract: FB12 FB13 PQ160 XC7300 XC73144 MC39I MC3 117 MC14-4
Contextual Info: XC73144 144-Macrocell CMOS EPLD  Product Specifications Features The Universal Interconnect Matrix connects the Function Blocks to each other and to all input pins, providing 100% connectivity between the Function Blocks. This allows logic functions to be mapped into the Function Blocks and

MC136

Contextual Info: S I XILINX XC73144 144-Macrocell CMOS CPLD June 1,1996 Version 1.0 Product Specification Features description. To minimize power dissipation, unused Func­ tion Blocks are turned off and unused macrocells in used Function Blocks are configured for low power operation.