X0Y80 Search Results

X0Y80 Datasheets Context Search

Catalog Datasheet	Type	Document Tags	PDF
CLK180 Abstract: MULT18X18 XAPP622 XC2V3000-FF1152 XC2V3000FF1152 sdr receiver Contextual Info: Application Note: Virtex-II Series R 644-MHz SDR LVDS Transmitter/Receiver Author: Ed McGettigan XAPP622 v1.2 July 2, 2002 Summary This application note describes single data rate (SDR) transmitter and receiver interfaces operating at up to 644 MHz, using 17 Low-Voltage Differential Signaling (LVDS) pairs (one	Original	644-mhz xapp622 xc2v3000-ff1152 clk180 +3mult18x18 xc2v3000ff1152 sdr receiver	PDF
RTL 8188 Abstract: RAMB18SDP RAMB36 UG190 XC5VLX XC5VLX220T XC5VLX85T RAM32X1D SRLC32E xilinx jtag cable spartan 3 Contextual Info: Virtex-5 FPGA User Guide UG190 v5.2 November 5, 2009 Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit the	Original	ug190 sstl18 rtl 8188 ramb18sdp +7ramb36 xc5vlx xc5vlx220t xc5vlx85t ram32x1d srlc32e xilinx jtag cable spartan 3	PDF
RTL 8188 Abstract: RAMB18SDP differential amplifier cascade output UG190 vhdl code hamming ecc t3 bel 187 TRANSISTOR REPLACEMENT GUIDE 20303 RAMB36 FPGA Virtex 6 Contextual Info: Virtex-5 FPGA User Guide UG190 v5.0 June 19, 2009 Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit the	Original	ug190 sstl18 rtl 8188 ramb18sdp +7differential amplifier cascade output vhdl code hamming ecc t3 bel 187 transistor replacement guide 20303 ramb36 fpga virtex 6	PDF
RTL 8188 Abstract: UG190 RAMB36 301071207 DO310 TRANSISTOR REPLACEMENT GUIDE XC5VLX220T XC5VLX85T RAMB18SDP Contextual Info: Virtex-5 FPGA User Guide UG190 v4.4 December 2, 2008 R R Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit the	Original	ug190 sstl18 rtl 8188 ramb36 +6301071207 do310 transistor replacement guide xc5vlx220t xc5vlx85t ramb18sdp	PDF
RTL 8188 Abstract: RAMB18SDP xerox 1025 ISERDES Virtex-5 FPGA User Guide UG190 RAMB36 vhdl code hamming ecc RAMB36SDP RAMB18 UG190 Contextual Info: Virtex-5 FPGA User Guide UG190 v5.3 May 17, 2010 Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit the	Original	ug190 sstl18 rtl 8188 ramb18sdp +7xerox 1025 iserdes virtex-5 fpga user guide ug190 ramb36 vhdl code hamming ecc ramb36sdp ramb18	PDF
XC2V3000-FF1152 Abstract: XC2V3000FF1152 XAPP622 CLK180 MULT18X18 7SV11 Contextual Info: Application Note: Virtex-II Series R 644-MHz SDR LVDS Transmitter/Receiver XAPP622 v1.4 August 5, 2003 Summary This application note describes single data rate (SDR) transmitter and receiver interfaces operating at up to 644 MHz, using 17 Low-Voltage Differential Signaling (LVDS) pairs (one	Original	644-mhz xapp622 xc2v3000-ff1152 xc2v3000ff1152 +3clk180 mult18x18 7sv11	PDF
12-bit ADC interface vhdl code for FPGA Abstract: iodelay ISERDES XC5VLX50T-FF1136.xls VHDL code for high speed ADCs using SPI with FPGA 12-bit ADC interface vhdl complete code for FPGA virtex 4 date code for ADC XAPP866 iodelay for adc parallel data and fpga interface UCF virtex-4 Contextual Info: Application Note: Virtex-4 and Virtex-5 FPGAs R XAPP866 v3.0 April 7, 2008 An Interface for Texas Instruments Analog-to-Digital Converters with Serial LVDS Outputs Author: Marc Defossez Summary This application note describes how to interface a Texas Instruments analog-to-digital	Original	xapp866 12-bit adc interface vhdl code for fpga iodelay iserdes +6xc5vlx50t-ff1136.xls vhdl code for high speed adcs using spi with fpga 12-bit adc interface vhdl complete code for fpga virtex 4 date code for adc iodelay for adc parallel data and fpga interface ucf virtex-4	PDF
XC2V3000-FF1152 Abstract: XAPP622 Digital clock MODULE CIRCUIT DIAGRAM CLK180 MULT18X18 X0Y80 XC2V3000FF1152 Contextual Info: Application Note: Virtex-II Series R 644-MHz SDR LVDS Transmitter/Receiver XAPP622 v1.7 April 27, 2004 Summary This application note describes single data rate (SDR) transmitter and receiver interfaces operating at up to 644 MHz, using 17 Low-Voltage Differential Signaling (LVDS) pairs (one	Original	644-mhz xapp622 xc2v3000-ff1152 cs144 +10fg256 fg456 fg676 bg575 bg728 digital clock module circuit diagram clk180 mult18x18 x0y80 xc2v3000ff1152	PDF