VOH0 Search Results

80C51

Abstract: 80C52 PDIL40 PLCC44 TS80C51U2 TS83C51U2 TS87C51U2 VQFP44 16kx8 ram
Contextual Info: TS80C51U2 TS83C51U2 TS87C51U2 Double UART 8-bit CMOS Microcontroller 1. Description TS80C51U2 is high performance CMOS ROM, OTP and EPROM versions of the 80C51 CMOS single chip 8-bit microcontroller. The TS80C51U2 retains all features of the 80C51 with extended ROM/EPROM capacity 16 Kbytes , 256 bytes

jeida+dram+88+pin

Abstract: jeida 88 pin jeida dram 88 pin
Contextual Info: STI321000C1 -xxVx 88-PIN CARDS 1M X 32 DRAM Card FEATURES • Performance range: ^RAC ^CAC *RC STI321000C1-60Vx 60ns 15ns 110ns STI32100OC1-7OVx 70ns 18ns 130ns STI321000C1-80Vx 80ns 20ns 150ns The Simple Technology STI321000C1 is a 1M bit x 32 Dynamic RAM high density memory card. The Simple Technology

Contextual Info: Spansion Analog and Microcontroller Products The following document contains information on Spansion analog and microcontroller products. Although the document is marked with the name “Fujitsu”, the company that originally developed the specification, Spansion

10E1

Abstract: 10E2 20E1 20E2 SN54AHCT16540 SN74AHCT16540
Contextual Info: SN54AHCT16540, SN74AHCT16540 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS S C LS 338D - M ARCH 1996 - REVISED JULY 1997 • • • • • • • • Inputs Are TTL-Voltage Compatible Members of the Texas Instruments Widebus Family EPIC™ Enhanced-Performance Implanted

Contextual Info: TIBPAL22V10-7C, TIBPAL22V10-10M HIGH-PERFORMANCE IMPACT-X PROGRAMMABLE ARRAY LOGIC CIRCUITS SRPS014B - D3620, A U G U S T 1990 - REVISED SEPTEMBER 1992 C SUFFIX. . NT PACKAGE M SUFFIX. . JT PACKAGE TOP VIEW Second-Generation PLD Architecture High-Performance Operation:

Contextual Info: HD74ALVC16834 18-bit Universal Bus Driver with 3-state Outputs and Inverted Latch Enable HITACHI ADE-205-216C Z Preliminary, 4th. Edition Jan. 1, 1999 Description The HD74ALVC16834 is an 18-bit universal bus driver designed for 2.3 V to 3.6 V Vcc operation.

Contextual Info: in te l M80C51FB CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLER MiHtary M80C51FB — 3.5 MHz to 12 MHz, VCc = 5V ± 10% M80C51FB-16 — 3.5 MHz to 16 MHz, Vcc = 5V ± 10% High Performance CHMOS EPROM 32 Programmable I/O Lines Three 16-Bit Timer/Counters 7 Interrupt Sources

P87C575EHAA I

Abstract: P83C575EHPN 80C51 80C575 83C575 87C575 EC20D 2031h
Contextual Info: Philips Semiconductora Microcontroller Product 7 1 1 □ fl 2 b 0□bbb03 CMOS single-chip 8-bit microcontroller Product specification PHIN 80C575/83C575/87C575 • 80C51 based architecture - 8k x 8 ROM 83C575) - 8k x 8 EPROM (87C575) - ROMIess (80C575)

ICT 20 PIN PLASTIC 300 MIL DIP

Abstract: 22V10 complete details 22CV10AZ 22CV10A PAL22V10 PEEL22CV10AZJ-25 PEEL22CV10AZP-25 PEEL22CV10AZPI-25 PEEL22CV10AZS-25 PEEL22CV10AZT-25
Contextual Info: Commercial/ Industrial PEEL 22CV10AZ -25 CMOS Programmable Electrically Erasable Logic Device Features • Ultra Low Power Operation - VCC = 5 Volts ±10% - Icc = 10 µA typical at standby - Icc = 2 mA (typical) at 1 MHz - tPD = 25ns. ■ CMOS Electrically Erasable Technology

AT8C51

Abstract: 80C51 AT83C5103 AT87C5103 SSOP16 SSOP24
Contextual Info: Features • • • • • • • • • • • • • 80C51 Compatible CPU Core High-speed Architecture X2 Speed Improvement Capability 6 Clocks/Machine Cycle 16 MHz in Standard or X2 mode 256 Bytes RAM 256 Bytes XRAM 12K Bytes ROM/OTP Program Memory

Contextual Info: Lattice ispLSI and pLSI 1048E ; Semiconductor I Corporation High-Density Programmable Logic Features Functional Block Diagram • HIGH DENSITY PROGRAMMABLE LOGIC O u tpu t R outing Pool — 8,000 PLD Gates | | O u tpu t R outing Pool ü m u lü lü llS i!

5962-0051801VQC

Abstract: sc80c32 80C32 80C32E 80C52 SB40 SC80C32E
Contextual Info: Features • • • • • • • • • • • • • • • • • • • 8032 pin and instruction compatible Four 8-bit I/O ports Three 16-bit timer/counters 256 bytes RAM Full duplex UART Asynchronous port reset 6 sources, 2 level interrupt structure

Contextual Info: Features • Bipolar Speed in JEDEC Standard EPROM Pinout Read Access Time • 55ns 28-Lead 600 mil CERDIP and OTP Plastic DIP 32-Pad LCC, JLCC and OTP PLCC • Low Power CMOS Operation 100 jiA max. Standby 50 mA max. Active at 10 MHz • High Output Drive Capability

Contextual Info: TO SHIBA ADVANCE INFORMATION TC74VCX16841 FT TOSHIBA CMOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC Tf74UfY1fiRdlFT LOW-VOLTAGE 20-BIT D-TYPE LATCH WITH 3.6V TOLERANT INPUTS AND OUTPUTS The TC74VCX16841 FT is a high performance CMOS 20-bit D-TYPE LATCH. Designed for use in 1.8, 2.5 or 3.3 Volt

Contextual Info: Lattice ispLSI’ and pLSI’ 2096V ; ” Semiconductor • ■ ■ Corporation 3.3V High-Density Programmable Logic Features Functional Block Diagram* • HIGH DENSITY PROGRAMMABLE LOGIC is»« r r m i n n r a n — — — — — 4000 PLD Gates 96 I/O Pins, Six Dedicated Inputs

Contextual Info: PRELIMINARY in te i 8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER Commercial/Express • User-selectable Configurations: — External Wait States 0-3 wait states ■ Real-time and Programmed Wait State Bus Operation ■ Binary-code Compatible with MCS> 51

2Y16

Contextual Info: HD74ALVC16830 1-bit to 2-bit Address Driver with 3-state Outputs HITACHI ADE-205-198 Z Preliminary 1st. Edition November 1997 Description This 1-bit to 2-bit address driver is designed for 2.3 V to 3.6 V V cc operation. To ensure the high impedance state during power up or power down, the output ebable (OE) input should be tied to V cc

Contextual Info: in y A W Ä N K D H 0M F Ö 3G fflA T D {K ] 8XC51RA/RB/RC CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLER Commercial/Express *See Table 1 for Proliferation Options High Performance CHMOS EPROM/ ROM/CPU

AT8C51

Contextual Info: Features • • • • • • • • • • • • • 80C51 Compatible CPU Core High-speed Architecture X2 Speed Improvement Capability 6 Clocks/Machine Cycle 16 MHz in Standard or X2 mode 256 Bytes RAM 256 Bytes XRAM 12K Bytes ROM/OTP Program Memory

87c510

Abstract: 80C51 SO24 SSOP24 T83C5101 T83C5102 T87C5101
Contextual Info: Features • 80C51 Code Compatible • • • • • • • • • • • • • – 8051 Instruction Compatible – 16 I/O + 2 Outputs in 24 Pin Packages 16 I/O + 6 Outputs in 28 Pin Packages – Three 16-bit Timer/Counters – 256 Bytes Scratchpad RAM

HP4396B

Abstract: IDTVS512
Contextual Info: DATASHEET WIDE BANDWIDTH VIDEO SIGNAL SWITCH, 5 PORT General Description Features The IDTVS512 is a bi-directional 5-Port 2:1 multiplexer/demultiplexer with Hi-Z outputs for both RGB and composite video switching applications. With the additional two ports, vertical and horizontal synchronous

c code for 8051 interfacing with AT24C02

Abstract: 8051 pure sine PWM 8051 interfacing with AT24C02 8051 microcontroller pin configuration 8051 Family with internal ADC 8051 interfacing to EEProm a to d converter interface with 8051 interfacing 8051 with eeprom c source code 8051 basics 8051 reset circuit
Contextual Info: Features • 80C51 Compatible • • • • • • • • • • • • • • • – Two I/O Ports – Two 16-bit Timer/Counters – 256 bytes RAM 4 Kbytes ROM or 4 Kbytes Flash Program Memory 256 bytes EEPROM Stack Die Packaging Technology on SO20 Package

CM2009-02QR

Abstract: vga to video circuit diagram schematic diagram vga to component video dvi schematic CM2009 Non VGA Video Controller IC schematic diagram video to vga vga connector CM2009-00QR CM2009-00QS
Contextual Info: CM2009 VGA Port Companion Circuit Features Product Description • The CM2009 connects between a video graphics controller embedded in a PC, graphics adapter card or set top box and the VGA or DVI-I port connector. The CM2009 incorporates ESD protection for all signals,

Contextual Info: To our customers, Old Company Name in Catalogs and Other Documents On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the old company name remains in this document, it is a valid