VLSI TECH Search Results

Contextual Info: TB92-002 TECHNICAL BULLETIN TranSwitch VLSI Devices VLSI Device Pins With No Internal Connection VLSI Device Pins With No Internal Chip Connection Should Be "Open" On The PC Board VLSI device pins now with no internal VLSI connection identified in the TranSwitch VLSI Data Sheets as NC No Connection may in future releases of the device be internally connected to integrated circuits added within the

Contextual Info: VLSI Techn VMS115 >iogy Data Sheet VLSI T e ch no l og y VMS115 Data Sheet Revision: 2.0 VLSI Technology, Incorporated 1/28/99 Rev. 2.0 VMS11S VLSI ^ Data Sheet Technology Table o f Contents 1 2 3 4 5 6 Introduction .4

Contextual Info: VM S115 VLSI Data Sheet Techn >iogy VLSI Technology V M S 1 1 5 Data Sheet Revision: 2.0 VLSI Technology, Incorporated 1/28/99 Rev. 2.0 VM S11S VLSI ^ Data Sheet Technology Table of Contents 1 2 3 4 5 6 I n tr o d u c tio n .4

Contextual Info: VMS113 VLSI Techn >iogy Data Sheet VLSI Technology V M S 1 1 3 Data Sheet Revision: 2.1 VLSI Technology, Incorporated 2/5/99 Rev. 2.1 VMS113 VLSI ^ T e c h no l og y Data Sheet Revision History Dull1 *hanj»i‘s U e\ision 1/28/99 Baseline Version 2.0 2/5/99

TXC-03001-AIPL

Abstract: TXC-03001-BIPL TB-516
Contextual Info: TB-516 TECHNICAL BULLETIN SOT-1 VLSI Device, TXC-03001B Differences Between the “A” and “B” Versions of the SOT-1 VLSI Device PURPOSE OF THIS TECHNICAL BULLETIN TranSwitch is introducing a “B” version of the 84-pin SOT-1 VLSI device, which emulates the features and

VMS113

Abstract: "vlsi technology"
Contextual Info: VLSI Techn VMS113 Data Sheet >i ogy VLSI Technology VMS113 Data Sheet Revision: 2.1 VLSI Technology, Incorporated 2/5/99 Rev. 2.1 VMS113 VLSI ^ Technology Data Sheet Revision History Dcik- WÈÈÈÈÈÈÈÈÈÈÈÈÈÈÈÈÈÈÈÊÈÊÊÈÈÊÈÊÈÈÈÈÈÈÈÈÈÈÈÈÈÈÈÈÈÈÈÈÈÈ

VLSI Technology

Abstract: 7MPV6186 D2382 burndy connector burndy grounding terminal
Contextual Info: 256KB AND 1MB SECONDARY CACHE MODULES FOR THE INTEL PENTIUM CPU/VLSI 82C590 CORE LOGIC PRELIMINARY IDT7MPV6186 IDT7MPV6187 Integrated Device Technology, Inc. FEATURES DESCRIPTION • 256KB/1MB 3.3V asynchronous secondary cache module family for the VLSI 82C590 core logic chipset

VL82c311

Abstract: VL82C48 vl82c486
Contextual Info: VL82C425 CACHE MEMORY CONTROLLER O v e r v ie w VLSI Technology, Inc.'s VL82C425 is a high-performance, highintegration, single-chip secondlevel cache memory controller for use in the design of 486-based PC/AT-compatible systems. When used with the VLSI SC486

64K X 4 CACHE SRAM

Abstract: CELP2X80SC3Z48 CARD-EDGE IDT7MPV6186
Contextual Info: 256KB AND 1MB SECONDARY CACHE MODULES FOR THE INTEL PENTIUM CPU/VLSI 82C590 CORE LOGIC PRELIMINARY IDT7MPV6186 IDT7MPV6187 Integrated Device Technology, Inc. FEATURES DESCRIPTION • 256KB/1MB 3.3V asynchronous secondary cache module family for the VLSI 82C590 core logic chipset

VMS110

Abstract: VLSI TECHNOLOGY VMS113
Contextual Info: 906 Data Sheet VMS113 Data Sheet Revision: 2.1 VLSI Technology, Incorporated 2/5/99 Rev. 2.1 906 Data Sheet Revision History Date Changes Revision 1/28/99 Baseline Version 2.0 2/5/99 Updated AC Paramters: TADDRH; TDIOH; TRWH 2.1 VLSI Technology, Incorporated

TXC-04001-BIPL

Abstract: TXC-04001-AIPL TXC-04011-BIPQ
Contextual Info: TB-512 TECHNICAL BULLETIN ADMA-T1 VLSI Device, TXC-04001 Differences Between the “A” and “B” Versions of the ADMA-T1 Device PURPOSE OF THIS TECHNICAL BULLETIN TranSwitch has introduced a “B” version of the ADMA-T1 VLSI device, which is a dual T1 mapper that

TXC-04002-AIPL

Abstract: TXC-04002-BIPL TranSwitch Corporation
Contextual Info: TB-518 TECHNICAL BULLETIN ADMA-E1 VLSI Device, TXC-04002B Differences Between the “A” and “B” Versions of the ADMA-E1 Device PURPOSE OF THIS TECHNICAL BULLETIN TranSwitch has introduced a “B” version of the ADMA-E1 VLSI device, TXC-04002B, which has some

V/VGT200017

Contextual Info: VLSI T ec h n o lo g y in c . GATE ARRAY PRODUCTS GATE ARRAY BASES FEATURES DESCRIPTION • High reliability - over 2000 V protection against Electrostatic Discharge ESD VLSI Technology’s VGT Series of high-performance and hlgh-density gate arrays utilize the Company’s

qualcomm aT commands

Abstract: Q4400 qualcomm 7200 qualcomm IQ Qualcomm DDS viterbi algorithm qualcomm AT Command
Contextual Info: I Preliminary Technical Data Sheet for the Q4400 Variable Rate Vocoder Q ualco /w sa ^ 9 - VLSI Products 10555 Sorrento Valley Road San Diego, CA USA 92121-1617 Phone: 619 597-5005 FAX: (619) 452-9096 March 1993 DL80-3749-8 X2 a Other QUALCOMM VLSI Products

NRF2401

Abstract: nRF2402 nRF240X hearing aid chip 2.4Ghz RF Remote control transmitter receiver NRF M 24 DEMO TX AUDIO
Contextual Info: nRF240X - Nordic VLSI 2,4GHz Components for wireless communication Introducing the 2.4GHz nRF2401 transceiver and nRF2402™ transmitter. The nRF2401 and nRF2402 are the first wireless components from Nordic VLSI ASA manufactured in an ultra modern 0.18µm,

8251 uart

Abstract: SERIAL CONTROLLER 8251 VNS80000 vlsi vlsi cmos circuitry VNS8000 UART 8251 VLSI Solution implement codec G.711 8251 programmable communication interface
Contextual Info: Networking Communications VIP Single-Chip VLSI ISDN Subscriber Processor OVERVIEW F E AT U R E S The VLSI ISDN Subscriber Processor VIP offers in a single device a powerful programmable engine for ISDN subscriber communications. It includes most of the circuitry

k3155

Abstract: MCR68-3 DT28
Contextual Info: M13X Device DS3/DS1 MUX/DEMUX, Enhanced Features TXC-03305 FEATURES DESCRIPTION • The The M13X M13X CMOS CMOS VLSI VLSI device device provides provides the the functions functions needed needed to to multiplex multiplex and and demultiplex demultiplex 28

71B74

Abstract: IDT71B74 Intel Pentium 66MHz 1993
Contextual Info: N E W S R E L E A S E FOR IMMEDIATE RELEASE FOR FURTHER INFORMATION: Stewart Sando, Director of SRAM Marketing 408 754-4607 Tami Maggio, Public Relations Specialist Jim Lipman, Public Relations Manager, VLSI Technology (408) 492-8699 (408) 434-7673 IDT AND VLSI TECHNOLOGY TEAM TO PROVIDE

CONDITIONS31

Abstract: B1274 1553B UT1553 what about 1553 bus
Contextual Info: UT1553 Remote Terminal Multi-Protocol FEATURES INTRODUCTION ❐ Complete VLSI MIL-STD-1553 Remote Terminal The UT1553 RTMP figures 1 and 4 is a monolithic, CMOS, VLSI integrated circuit that meets all requirements for a dual-redundant MIL-STD-1553 Remote Terminal

UT1553B

Abstract: 1553b rti CHA Series mil-std-1553b SPECIFICATION 1553B UT1553 RTMP rta2
Contextual Info: UT1553 Remote Terminal Multi-Protocol FEATURES INTRODUCTION ❐ Complete VLSI MIL-STD-1553 Remote Terminal The UT1553 RTMP figures 1 and 4 is a monolithic, CMOS, VLSI integrated circuit that meets all requirements for a dual-redundant MIL-STD-1553 Remote Terminal

full subtractor using NOR gate for circuit diagram

Abstract: full subtractor circuit using nor gates AX277 2 bit full adder SIGNAL PATH DESIGNER full subtractor circuit using nand gate
Contextual Info: VITESSE SEMICONDUCT OR 30E D H '1502331 GODDeTb 5 * V T S T -M -H ! Features • VLSI Complexity: > 35,000 Gates •Very Low Power Disspation • Superior Performance: 300M Hz to 3 GHz ■High Yielding, 4 Layer Metal, VLSI Process • Choice of Operating Temperature Ranges:

rta2

Contextual Info: UT1553 Remote Terminal Multi-Protocol FEATURES INTRODUCTION ❐ Complete VLSI MIL-STD-1553 Remote Terminal The UT1553 RTMP figures 1 and 4 is a monolithic, CMOS, VLSI integrated circuit that meets all requirements for a dual-redundant MIL-STD-1553 Remote Terminal

LT 410

Abstract: LT 412 pin diagram for core i7 processor 7MPV6186
Contextual Info: ^g g g a ^ s 256KB AND 1 MB SECONDARY CACHE MODULES FOR THE INTEL® PENTIUM CPU/VLSI 82C590 CORE LOGIC I p eft/ ^T7MPV6186 iDT7MPV6187 Integrated Device Technology, Inc. FEATURES DESCRIPTION • 256KB/1 MB 3.3V asynchronous secondary cache module family for the VLSI 82C590 core logic chipset

Contextual Info: t r ä n S w it c h -X-TB-524 TECHNICAL BULLETIN QEIM VLSI Device, TXC-04252 PRODUCT PREVIEW Plastic Ball Grid Array Package Option for OE1M Device PURPOSE OF THTS TECHNICAL BULLETIN TranSwitch is introducing an additional package option for the QEIM Quad E l Mapper VLSI Device. The